A kind of ldmos device and preparation method thereof

Abstract

The present invention proposes an LDMOS device, which includes a semiconductor substrate, a buried layer, an epitaxial layer, a source metal, a drain metal, and a field oxide layer. Body region and N-type semiconductor drain region, the left half of the PN variable doping field drop layer is a P-type variable doping region, and the right half is an N-type variable doping region, and the P-type variable doping region is The P-type impurity concentration gradually decreases from left to right to 0 cm ‑3 , the N-type impurity concentration in the N-type variable doping region gradually decreases from right to left to 0 cm ‑3 . By preparing a PN variable doping drop field layer in the epitaxial layer, a uniform electric field distribution is generated in the middle of the drift region, and at the same time, the high electric field peak at the main junction is eliminated, and the surface electric field distribution in the drift region is optimized, thereby improving the device. In addition, the PN variable doping field drop layer can increase the concentration of the drift region of conventional devices, effectively improving the current capability of the device and reducing the on-resistance of the device.

Description

technical field [0001] The invention relates to an LDMOS device and a preparation method thereof, belonging to the technical field of integrated circuits. Background technique [0002] With the development of power electronics technology, power integrated circuits have put forward higher requirements on the performance of semiconductor power devices. As the core device of power integrated circuits, lateral semiconductor power devices need to provide high withstand voltage and low on-resistance . LDMOS (Laterally Diffused Metal Oxide Semiconductor Transistor) is widely used due to its good process compatibility and easy monolithic integration of the source, gate and drain distributed on the surface with low-voltage logic circuits through internal wiring. However, when the breakdown voltage of LDMOS increases, the on-resistance often increases at the same time. This contradictory relationship limits the application of this type of device in the field of high voltage and high...

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Problems solved by technology

The P-type PN variable-doping field-reducing layer B13 is located in the N-type epitaxial layer B3. The P-type PN variable-doping field-reducing layer B13 can reduce the on-resistance of the LDMOS device to a certain extent, but due to the distribution of the surface electric field It can be seen that there will be an electric field trough at the forward biased PN junction, which will affect the electric field distribution on the surface of the device.

In addition, in order to optimize the surface electric field distribution, the PN variable doping field drop layer B13 should be as close as possible to the P-type semiconductor body region B4. The current channel between the two decreases as the distance between the two decreases, so it will cause Increase the on-resistance, these shortcomings seriously affect the further improvement of the device's operating voltage

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