Non-volatile memory reading circuit and reading method

Abstract

The invention provides a non-volatile memory reading circuit and a non-volatile memory reading method, and the circuit comprises a nanosecond-level charging pulse generation module which generates a post-charging pulse signal; a charging voltage generation module which generates a post-charging voltage; a bit line reading charging module which is used for charging a bit line to be read; a first reference read voltage generation circuit which charges the reference read bit line and generates a reference read current and a first reference read voltage; and a sense amplifier which is used for comparing the reference read current with the read current to generate a read voltage signal. According to the invention, the rising speed of the reading bit line voltage is improved, the peak value of the reading current is reduced, the dynamic power consumption is reduced, and the time required for the reading current and the reference reading current to reach stable values is reduced; and matching of parasitic parameters is introduced into the reference reading current, matching of parasitic parameters of the current mirror is introduced into the reading current, and post-charging operation is carried out on the reading bit line and the reading reference bit line, so that the pseudo reading phenomenon is eliminated to the maximum extent, and the reading time is reduced.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a nonvolatile memory readout circuit and a readout method. Background technique [0002] In the field of integrated circuit manufacturing, as the process nodes continue to shrink, traditional charge-based memories are increasingly limited. Various new memories and new structures have been invented to break through the original limits: MLC NAND, MLC NOR, TLC NAND, MRAM, RRAM, FeRAM, 3D-Xpoint, 3D-NAND, etc. The read latency of traditional and new memories is different: for SRAM as memory, the read time of DRAM is within 10ns, that of NAND Flash is around 50us, that of 3D-NAND is around 500us, and that of hard disk is around 10ms. If the read time of the memory can be further mined, its competitiveness will be greatly improved. [0003] Phase Change Memory (Phase Change Memory, PCM) is a memory based on the Ovshinsky electronic effect proposed by Ovshinsky in the late...

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Problems solved by technology

[0007] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a non-volatile memory readout circuit and a readout method, which are used to solve the problem of excessively long readout time and dynamic power consumption of the non-volatile memory in the prior art. Too big and other problems

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