Process execution control method, device, computer equipment and storage medium

Abstract

The invention discloses a process execution control method, a process execution control device, computer equipment and a storage medium. The method comprises the steps: obtaining a process execution control request which comprises a design identification and a target process node; querying a system database based on the design identifier, and obtaining a tree-shaped dependency relationship table;if the node state corresponding to the target process node is a to-be-executed state, adding the target process node to a first-in last-out queue; querying a tree-shaped dependency relationship tablebased on the target process node, and obtaining all preorder dependency nodes corresponding to the target process node and a node state corresponding to each preorder dependency node; and according tothe process dependency relationship, sequentially adding the preorder dependency nodes of which the node states are the to-be-executed states to a first-in last-out queue, and obtaining a process node execution queue. According to the method, the FPGA design and development period is effectively shortened. The FPGA design and development efficiency is improved, and the design and development costis reduced.

Description

technical field [0001] The present invention relates to the technical field of FPGA design process, in particular to a process execution control method, device, computer equipment and storage medium. Background technique [0002] The design process of FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) is the process of developing FPGA chips using EDA (Electronics Design Automation, electronic design automation) development software and programming tools. The development process of a typical FPGA generally includes function definition / device selection, design input, function simulation, synthesis optimization, post-synthesis simulation, layout and routing, timing simulation, chip programming, and debugging. It can be seen that a complete FPGA design needs to execute a series of processes, that is, each FPGA design needs to execute at least two original process nodes and there is a dependency relationship between two adjacent original process nodes; the parame...

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Problems solved by technology

[0004] Embodiments of the present invention provide a process execution control method, device, computer equipment, and storage medium to solve the problem of how to improve the efficiency of chip design and development while ensuring the maintainability and scalability of design and development

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