Encapsulation structure and method for forming same

Abstract

A packaging structure and its forming method, the forming method provides a number of semiconductor chips, each semiconductor chip has a pad on the functional surface, a metal bump is formed on the surface of the pad, and the functional surface also has a first A plastic sealing layer, the first plastic sealing layer covers the metal bumps; the non-functional surfaces of the semiconductor chips are bonded to the carrier; the side walls covering the semiconductor chips are formed on the carrier and the second plastic layer of the first plastic layer on the non-functional surface; planarizing and removing part of the first plastic layer and the second plastic layer on the carrier board, exposing the top surface of the metal bump; External contact structures connected with metal bumps are formed on the surfaces of the planarized first and second plastic encapsulation layers. The method of the invention improves the electrical connection performance between the rewiring layer and the welding pad in the packaging structure.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a fan-out packaging structure and a forming method thereof. Background technique [0002] Chip fan-in packaging is a manufacturing method in which rewiring and solder ball bumps are prepared on the entire wafer, and finally cut into individual chips. The final package size of this kind of package is equivalent to the chip size, which can realize the miniaturization and light weight of the package, and has a wide range of applications in portable devices. Although chip fan-in packaging can greatly reduce the packaged chip size, the number of balls on a single chip is limited, and this wafer packaging form is difficult to apply to chips with high-density I / O ports. Therefore, for chips with relatively high I / O density, if wafer-level packaging is performed, in order to ensure that the chip to be packaged and the printed circuit board can form an interconnection, the high...

AI Technical Summary

Problems solved by technology

[0004] However, in the packaging structure formed by the existing chip fan-out packaging process, the electrical connection between the wiring layer and the semiconductor chip is easily unstable, which affects the performance of the packaging structure.

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