Utilizing multilayer gate spacer to reduce erosion of semiconductor fin during spacer patterning

Abstract

FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).

Description

Technical field [0001] The present disclosure generally relates to semiconductor manufacturing technology, and in particular, to technology for manufacturing FET (Field Effect Transistor) devices. Background technique [0002] As semiconductor manufacturing technology continues to develop toward smaller design rules and higher integration density (for example, 14nm technology nodes and higher), integrated circuit devices and components become smaller and smaller, which are proposed in layout formation and device optimization Challenge. Currently, FinFET technology is usually used for FET manufacturing, because this type of technology provides an effective CMOS scaling solution for FET manufacturing at 14nm and below technology nodes. The FinFET device includes a three-dimensional fin-shaped FET structure that includes at least one vertical semiconductor fin structure formed on a substrate, a gate structure formed on a portion of the vertical semiconductor fin, and a vertical sem...

AI Technical Summary

Problems solved by technology

While the spacer RIE process can be tuned to minimize etch erosion of vertical semiconductor fins formed from silicon (Si) or silicon germanium (SiGe), the selectivity of the RIE process scales with fin pitch scaling (e.g., reducing fin inter-sheet spacing) and decreases as the height of the fin increases (e.g., the aspect ratio of the spacer RIE increases)

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