Anti-line crosstalk NAND gate circuit based on gate capacitor

Abstract

The invention discloses an anti-line crosstalk NAND gate circuit based on a gate capacitor. The circuit comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a low threshold inverter and two signal sampling circuits. The first MOS tube is used as a first capacitance value adjusting unit; the second MOS tube is used as a second capacitance value adjusting unit; the third MOS transistor and the fourth MOS transistor form a node isolation unit, the two signal sampling circuits form an anti-input interference unit, the low-threshold inverter forms a filtering unit, and the low-threshold inverter is used for filtering interference signals generated by capacitance output ends of the two capacitance adjusting units and outputting correct NAND logic signals. The anti-line crosstalk NAND gate circuit has the advantages that when the NAND gate circuit is adopted to design a chip, even if long-distance metal interconnection lines exist between the NAND gate circuits,the NAND gate circuit can still work normally, then it is guaranteed that the output logic of a functional module is correct, it is guaranteed that the whole chip can meet the functions required by design, and the robustness of the chip is enhanced.

Description

technical field [0001] The invention relates to a NAND gate circuit, in particular to a gate capacitance-based anti-line crosstalk NAND gate circuit. Background technique [0002] With the increasing demand for miniaturized digital circuits, more and more components are integrated to form compact functional modules, thus putting forward higher requirements for the integration of digital circuit systems. Metal interconnect lines are an important part of the CMOS manufacturing process. In digital circuit systems, due to the small space between metal interconnect lines, there are many problems, such as noise in the circuit. In order to alleviate the trend of increasing resistance caused by the increasingly smaller line width of metal interconnect lines, the industry has to increase the vertical height of metal interconnect lines, which makes the aspect ratio of metal interconnect lines increase with the process size. The shrinkage is gradually increasing. However, increasing ...

AI Technical Summary

Problems solved by technology

The traditional NAND gate circuit consists of two PMOS transistors and two NMOS transistors. When the actual physical long-distance interconnection between the NAND gate circuit is due to the effect of coupling capacitance, it is very susceptible to crosstalk noise interference and output errors. logic signal

Therefore, more and more attention has been paid to the malfunction of the NAND gate caused by the crosstalk of the long-distance metal interconnection, which leads to the failure of the chip.

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