Semiconductor device and manufacturing method thereof
A manufacturing method and semiconductor technology, which are applied in the manufacturing of semiconductor/solid-state devices, semiconductor devices, electric solid-state devices, etc., can solve the problems of adverse effects on the performance of semiconductor devices, large parasitic capacitance, etc., and achieve the effect of improving performance and reducing parasitic capacitance.
Inactive Publication Date: 2020-01-24
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology
However, the parasitic capacitance between the epitaxial layer and the metal gate of the gate all-around (GAA) field effect transistor is large, which adversely affects the performance of the semiconductor device
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[0045] In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.
[0046] It should be understood that the invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
[0047] It will be understood that when an element or layer is referred t...
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The invention provides a semiconductor device and a manufacturing method thereof. The method comprises the following steps that: a semiconductor substrate is provided, wherein the semiconductor substrate comprises a first area and a second area, a first fin and a second fin are formed on the semiconductor substrate in the first area and the second area respectively, and each of the first fin and the second fin comprise Si layers and SiGe layers which are stacked alternately; a first dummy gate stretching over the first fin and a second dummy gate stretching over the second fin are formed; first trenches are formed in two sides of the first dummy gate, and second trenches are formed in two sides of the second dummy gate; parts of the SiGe layers exposed by the side walls of the first trenches are removed, so that first grooves are formed, and parts of the SiGe layers exposed by the side walls of the second trenches are removed, so that second grooves are formed; first side walls fillingthe first grooves are formed; and first stress layers are formed in the first trenches. According to the semiconductor device and the manufacturing method thereof provided by the invention, parasiticcapacitance between the gate and the stress layer can be reduced, and the performance of the semiconductor device is improved.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof. Background technique [0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. Currently, as the semiconductor industry has advanced to nanotechnology process nodes in pursuit of high device density, high performance, and low cost, the fabrication of semiconductor devices is limited by various physical limits. [0003] As the dimensions of CMOS devices continue to shrink, manufacturing and design challenges have prompted the development of three-dimensional designs such as Fin Field Effect Transistors (FinFETs). Compared with the existing planar transistors, FinFET is an advanced semiconductor device for 20nm and below process nodes, which can effe...
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IPC IPC(8): H01L21/8238H01L27/092
CPCH01L21/823821H01L27/0924
Inventor 周飞
Owner SEMICON MFG INT (SHANGHAI) CORP