Trimming circuit and chip

Abstract

The invention discloses a trimming circuit and a chip. The trimming circuit comprises a control module which is used for generating a fuse selection signal and a fuse signal according to a trimming signal and a reference voltage signal, a fuse unit which comprises a plurality of fuse structures, each of which comprises a fuse and a switching tube which are connected between the fuse signal input end and the ground, arranged in an array, a selection module which is used for scanning the switching tubes of the plurality of fuse structures according to a preset sequence and gating at least one switching tube according to the fuse selection signal, wherein the trimming signal at least comprises a first level and a second level, and when the trimming signal is the first level, the control module generates the fuse selection signal; and when the trimming signal is a second level, the control module generates the fuse wire signal and is used for applying the fuse wire signal to the fuse wirewhen the switching tube is switched on. The trimming precision can be improved, and a specific trimming pin does not need to be arranged on the chip.

Description

technical field [0001] The invention relates to the field of integrated circuit design, and more specifically relates to a trimming circuit and a chip. Background technique [0002] With the development of integrated circuit technology and design technology, the circuit performance requirements are getting higher and higher, so as to meet a wide range of application requirements. However, circuit performance is always affected by the non-ideal factors of the semiconductor manufacturing process. These parasitic effects are mainly manifested in current mirror mismatch, absolute resistance deviation, temperature coefficient of resistance, resistor-capacitor mismatch, transistor mismatch, and packaging stress. Introduced drift and input offset voltage, etc., and these errors are random, so various trimming circuits for semiconductor operations will be reserved when designing chips. [0003] In order to realize high-precision analog integrated circuits on a standard process, pos...

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Problems solved by technology

[0005] Because of the instability of laser fuse trimming, the prior art usually uses wafer test trimming and wafer post-package trimming, but wafer test trimming and wafer post-package trimming have the following deficiencies: wafer test trimming Trimming is carried out before wafer packaging, but during wafer packaging, chip cutting and packaging will also affect the physical characteristics of the chip, resulting in deviations of the trimmed chip after packaging, which cannot meet the required accuracy; Trimming after wafer packaging requires the chip to have specific pins to apply the trimming signal, which puts higher requirements on the type of chip and cannot achieve mass production

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