Preparation method of stacked nanowire or sheet ring gate CMOS device

Abstract

The invention discloses a preparation method of a stacked nanowire or sheet ring gate CMOS device, which comprises the following steps: forming a plurality of fin-shaped structures on a semiconductorsubstrate along a first direction; wherein the fin-shaped structure comprises a fin part, a first material etching structure and a second material etching structure, and the first material etching structure and the second material etching structure are alternately stacked on the fin part; forming sacrificial gates, side walls and source / drain regions on the plurality of fin-shaped structures alonga second direction; removing the sacrificial gate; selectively removing the first material etching structure on the N well region in the gate region and the second material etching structure on the Pwell region; performing morphology adjustment processing on the remaining first material etching structure and the remaining second material etching structure to form a first channel region of the Pwell region and a second channel region of the N well region; passivating the first channel region and the second channel region to form an interface passivation layer; and forming a gate dielectric layer and a gate on the interface passivation layer. CMOS devices with N / PMOS corresponding to different conducting channels are prepared, and the performance of the devices is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor preparation, in particular to a preparation method of a stacked nanowire or sheet-ring-gate CMOS device. Background technique [0002] As the feature size of the device enters the 5nm technology node, small-scale quantum effects cause mobility degradation, and the saturation effect of strain engineering brought about by the continuous shrinking of the device causes the performance of the device to gradually degrade with the shrinking of the device size; SiGe Or Ge high-mobility materials have become a hotspot in the research of new three-dimensional devices because of their higher carrier mobility. [0003] However, if Ge-based NMOS devices are prepared, there are problems such as poor interface state, high source-drain contact resistance, low solid concentration of N-type impurities, and fast diffusion; therefore, SiGe or Ge high-mobility materials are generally used as conductive channels ...

AI Technical Summary

Problems solved by technology

[0004] In order to overcome the technical problem that the existing methods for preparing stacked nanowires or sheet-ring gate CMOS devices are difficult to realize the preparation of N / PMOS corresponding to different conductive channels, the present invention provides a stacked nanowire or sheet-ring gate CMOS Device fabrication method

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