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Multi-layer packaging substrate

A technology for packaging substrates and wiring layers, applied in electrical components, electrical solid devices, circuits, etc., can solve the problems of poor structural process yield and low process yield, and achieve the effect of ensuring yield and eliminating parasitic capacitance.

Active Publication Date: 2020-04-14
POWERTECH TECHNOLOGY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] In view of the disadvantages of poor structural process yield of the current multilayer packaging substrate, the main purpose of the present invention is to provide a new multilayer packaging substrate to overcome the shortcomings of the current low process yield

Method used

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Embodiment Construction

[0042] Below in conjunction with accompanying drawing, structural principle and working principle of the present invention are specifically described:

[0043] The invention aims at improving the structure of the multilayer packaging substrate used for chip packaging, so as to eliminate the influence of the parasitic capacitance existing between adjacent metal layers of the multilayer substrate on the transmission of high-speed signals. The technical content of the multi-layer packaging substrate of the present invention will be described in detail below with reference to the accompanying drawings. For the convenience of description, only the partial structure of the multi-layer packaging substrate will be described below.

[0044] See first Figure 1A As shown, it is the first preferred embodiment of the multilayer packaging substrate of the present invention. The multilayer packaging substrate 10 includes: a dielectric body 11, an external pad 12, a reference signal wiring l...

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Abstract

The present invention provides a multi-layer packaging substrate. The multi-layer packaging substrate comprises a dielectric body, an external pad, a reference signal wiring layer, a first conductivepost, a metal wiring layer and a signal wiring layer, wherein the external pad is formed on the bottom surface of the dielectric body and provided with bumps in a forming manner, the reference signalwiring layer and the signal wiring layer are formed on the dielectric body, the reference signal wiring layer forms a wiring space corresponding to the external pad and bumps thereof, the metal wiringlayer is formed in the wiring space, and the first conductive post is vertically formed in the dielectric body to connect the signal wiring layer and the external pad; and the metal wiring layer is connected to the first conductive post so as to have the same potential as the external pad and the bumps thereof corresponding to the lower part, thereby reducing the parasitic capacitance existing therebetween.

Description

technical field [0001] The present invention relates to a multilayer packaging substrate, especially a multilayer packaging substrate for high-speed chip packaging. Background technique [0002] In the semiconductor packaging process, the packaging substrate will be prepared in advance, and the chip will be soldered (for example: flip chip package, Flipchip package) or adhesively attached (for example: wire bonded package, Wirebonding package) on the package substrate, and then form a The encapsulant covering the chip forms a semiconductor packaging structure; since the bottom surface of the packaging substrate has a plurality of bumps, it can be welded to a system circuit board together with other electronic components; therefore, the packaging substrate is used as a chip and The medium for signal communication between system circuit boards. [0003] Since the multilayer packaging substrate contains multiple wiring layers, there will be parasitic capacitance between adjace...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/492H01L23/488H01L23/498
CPCH01L23/488H01L23/492H01L23/4924H01L23/49816H01L2224/11
Inventor 潘吉良周建玮
Owner POWERTECH TECHNOLOGY
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