Low-power-consumption transistor device with anti-radiation reinforced structure and preparation method thereof

Abstract

The invention discloses a low-power-consumption transistor device with an anti-radiation reinforced structure, which is characterized by comprising a substrate, a buried oxide layer located on the substrate, a bulk silicon layer located on the buried oxide layer, a source region, a drain region, a gate oxide layer located on the bulk silicon layer and a gate laminated structure located on the gateoxide layer, wherein the source region and the drain region are located in the bulk silicon layer and on the two sides of the bulk silicon layer, and the gate laminated structure sequentially comprises a lower polar plate metal layer, a ferroelectric layer and an upper polar plate metal layer from bottom to top or sequentially comprises a ferroelectric layer and an upper polar plate metal layer from bottom to top. According to the transistor device, the gate laminated structure is manufactured on the gate oxide layer, so that the channel potential is greater than the external grid voltage, the sub-threshold swing of 60mV / dec under thermodynamic limitation is broken through, the working voltage is reduced, and the power consumption of the device is reduced. Meanwhile, the source-drain junction depth with the same thickness as the bulk silicon layer is obtained through multiple times of step-by-step ion implantation, so that the source-drain junction is enabled to be in contact with theburied oxide layer at the bottom, and the single-particle irradiation resistance of the device is improved.

Description

technical field [0001] The invention relates to electronic device technology, and belongs to the technical fields of space environmental effects, nuclear science and low-power circuit application, and more specifically, relates to a low-power transistor device with a radiation-resistant hardened structure and a preparation method thereof. Background technique [0002] Space charged radiation particles mainly include heavy ions, electrons, protons and X-rays. These charged particles interact with transistor devices to produce ionizing radiation effects, single event effects, and displacement radiation effects. The traditional anti-radiation strengthening methods for devices usually use anti-radiation coatings or SOI technology. Among them, SOI is divided into fully depleted SOI and partially depleted SOI (PDSOI). For partially depleted SOI, It has a floating body effect, which leads to a parasitic diode amplification effect and increases the ability of sensitive storage node...

AI Technical Summary

Problems solved by technology

For fully depleted SOI, it can reduce the ability of sensitive storage nodes to collect radiated charges, but it has high requirements for the thickness of the top silicon layer, which is difficult and costly to realize in the process

[0003] At the same time, with the improvement of integrated circuit integration, power consumption and radiation resistance have become the main problems limiting its development, so it is urgent to develop radiation-resistant transistor devices with low power consumption

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