Logic circuit design method

Abstract

The invention discloses a logic circuit design method and apparatus, and a storage medium. The method comprises the steps of designing and generating an initial MOSFET-TFET hybrid logic circuit, wherein the MOSFET-TFET hybrid logic circuit comprises a plurality of logic gates; in a series branch of the initial MOSFET-TFET hybrid logic circuit, replacing a first type of TFET with an MOSFET, whereinthe first type of TFETs are directly grounded or connected with a power supply and are not directly connected with the output end of the logic gate. According to the logic circuit design method disclosed in the invention, by replacing the first type of TFET in the series branch of the initial logic circuit with the MOSFET, the defect of overlarge current attenuation caused by the TFET in the series branch is overcome, and the first type of TFET is a TFET which is directly grounded or powered and is not directly connected with the output end of the logic gate.

Description

technical field [0001] The present application relates to the technical field of integrated circuits, in particular to a method for designing logic circuits. Background technique [0002] In the past few decades, with the continuous shrinking of the size of semiconductor devices, the performance of integrated circuit chips has been continuously improved, but the power consumption of the system has gradually increased. This problem has slowed down the further reduction of device sizes. Since the subthreshold slope has a theoretical limit of 60mV / dec at room temperature, it is difficult for traditional MOSFET devices to continuously reduce the operating voltage V DD to reduce power consumption. MOSFET is Metal-Oxide Semiconductor Field-Effect Transistor, referred to as Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). In order to adapt to the future development trend of integrated circuits, research on new ultra-low power devices has attracted widespread attention....

AI Technical Summary

Problems solved by technology

[0003] However, the nonlinear turn-on characteristics of silicon-based TFETs lead to serious attenuation of current when they are connected in series. Once TFET devices are used in standard logic unit circuits (such as multi-input NAND gates, NOR gates, etc.), the series branch is too small. Currents severely degrade logic circuit performance, noise margin, etc.

Therefore, in order to reduce the power consumption of chip integrated circuits by using the ultra-steep sub-threshold slope and ultra-low off-state current characteristics of TFETs, it is necessary to overcome the shortcomings of excessive current attenuation when they are connected in series.

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