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Heterojunction bipolar transistor and preparation method thereof

A heterojunction bipolar and transistor technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of high production cost, long process development cycle, restrictions on SiGeHBT development and technology transformation, and reduce Development and production costs, reduction of collector width, and effects of reducing parasitic effects

Active Publication Date: 2020-06-05
YANSHAN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Although the performance of the device, especially its high-frequency characteristics, has been greatly improved, the long process development cycle and high production cost limit the development and technology transformation of SiGe HBT.

Method used

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  • Heterojunction bipolar transistor and preparation method thereof
  • Heterojunction bipolar transistor and preparation method thereof
  • Heterojunction bipolar transistor and preparation method thereof

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Embodiment Construction

[0051] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0052] like figure 1 As shown, the heterojunction bipolar transistor of the present invention selects a P-type doped single-crystal Si substrate whose crystal orientation is (110); epitaxy a layer of N+ doped single-crystal Si layer on the substrate as a buried layer ; A layer of N-doped single crystal Si layer is epitaxially deposited on the surface of the buried layer as the collector area; three STI structures with a thickness of 400nm are formed in the collector area to realize the isolation of the collector and the base, and the collector N+ doping is performed on the right side of the region; ion implantation is performed on the N-doped collector region, and P+ doping is formed on both sides as an extrinsic base region; a layer with a thickness of 1-2 μm is deposited on the device surface SiO 2 layer to define the position of the active region; selectively epita...

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Abstract

The invention provides a heterojunction bipolar transistor and a preparation method thereof. According to the heterojunction bipolar transistor, a emitter region and a base region have the same physical structure, so that the parasitic effect between the emitter region and the base region is effectively reduced, and the frequency characteristic of the device is improved; the width of the emitter region is 90 nanometers, so that the intrinsic resistance of the base region is effectively reduced; embedded SiGe structures are adopted on the two sides of a collector region; uniaxial strain is introduced while biaxial strain is conducted; the transmission time of carriers in the collector region is effectively shortened; the width of the effective collector region is reduced; collector junctioncapacitance is reduced; and the frequency characteristic of the device is further improved. The thickness of the Si cap layer is properly selected, so that the accumulation of carriers at the interface can be effectively reduced, and the gain of the device is improved. The preparation method of the bipolar transistor can be completely compatible with a 90-nanometer CMOS process, which effectivelyreduces the development and manufacturing cost of the device.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuits, in particular to a heterojunction bipolar transistor and a preparation method thereof. Background technique [0002] The CMOS process has entered the 7nm / 5nm node and is about to reach the end of the process development roadmap. In this context, the improvement of transistor performance mainly adopts strain engineering, high-K metal gate and transition from planar structure to three-dimensional structure. Starting from the 90nm process, the standard CMOS process mainly adopts the selective deposition method of SiGe layer in the source and drain regions, and introduces uniaxial stress in the channel region of the device. The introduction of stress can significantly increase the carrier mobility, thereby improving the performance of the device. However, in an actual circuit, as the size of the device decreases, the current driving capability of the device decreases, and ...

Claims

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Application Information

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IPC IPC(8): H01L29/737H01L29/08H01L21/331
CPCH01L29/7375H01L29/7378H01L29/0817H01L29/0821H01L29/66242H01L29/7371H01L29/1004H01L29/41708
Inventor 周春宇王冠宇常晓伟耿欣蒋巍谭金波
Owner YANSHAN UNIV