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Silicon-based buffer layer and preparation method thereof

A buffer layer, silicon-based technology, applied in the direction of final product manufacturing, sustainable manufacturing/processing, electrical components, etc., can solve the problem of large lattice difference between Si and CdTe materials, and achieve the suppression of twin formation, improve efficiency, The effect of improving quality performance

Inactive Publication Date: 2020-07-10
11TH RES INST OF CHINA ELECTRONICS TECH GROUP CORP
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Problems solved by technology

[0003] Embodiments of the present invention provide a silicon-based buffer layer and a preparation method thereof, which are used to solve the problem of large lattice differences between Si and CdTe materials, and improve the quality of CdTe substrate materials

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  • Silicon-based buffer layer and preparation method thereof
  • Silicon-based buffer layer and preparation method thereof

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preparation example Construction

[0036] Such as figure 1 As shown, the method for preparing a silicon-based buffer layer according to an embodiment of the present invention includes:

[0037] S1, obtaining Si (silicon) wafers that are atomically clean;

[0038] S2, turning on the As (arsenic) beam source and the Te (tellurium) beam source in sequence to passivate the front side of the Si sheet.

[0039] It can be understood that the As beam source is first turned on for a period of time to use As (arsenic) to passivate the front side of the Si sheet, thereby facilitating the growth of the B-side of the epitaxial material. Then turn on the Te beam source toward the front of the Si sheet for surface passivation, so as to keep the B-side growth of the epitaxial material.

[0040] S3, turn on the Zn (zinc) beam source and the Te beam source alternately, and epitaxially form a ZnTe buffer layer on the front side of the passivated Si sheet.

[0041] It can be understood that first turn on the Zn beam source for ...

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Abstract

The invention discloses a silicon-based buffer layer and a preparation method thereof. The preparation method of the silicon-based buffer layer comprises the following steps: obtaining an atomic-scaleclean Si wafer; sequentially opening an As beam source and a Te beam source, and passivating the front surface of the Si wafer; alternately opening a Zn beam source and a Te beam source, and extending a ZnTe buffer layer on the front surface of the passivated Si wafer; alternately opening a Zn beam source, a Te beam source and a CdTe beam source, and extending a ZnTe / CdTe superlattice buffer layer on the ZnTe buffer layer; and opening a Te beam source, and carrying out high-temperature annealing heat treatment on the ZnTe / CdTe superlattice buffer layer. According to the method, two independent raw material beam sources of Te and Zn are adopted for epitaxy, and are combined with an annealing process after epitaxy, so that the formation of twin crystals is inhibited, the process steps are effectively simplified, and the epitaxy efficiency is improved to a great extent. And a basic contribution is made to the development of a third-generation large-area-array infrared focal plane material.

Description

technical field [0001] The invention relates to the technical field of infrared detector preparation, in particular to a silicon-based buffer layer and a preparation method thereof. Background technique [0002] Due to the large lattice mismatch (19.3%) between the Si material and HgCdTe, a large number of threading dislocations are inevitably introduced during the epitaxy process. Usually, the composite substrate is formed by epitaxial cadmium telluride (CdTe) buffer layer on the surface of the Si wafer to reduce the lattice mismatch. However, due to the large lattice mismatch between the Si material and the CdTe material, in order to ensure the quality of the epitaxial material, control the epitaxial crystal orientation, and suppress the generation of dislocations, polycrystals, and twins, usually in the process of epitaxial CdTe materials A layer of buffer layer material will be epitaxy first. The buffer layer of the Si-based CdTe material is generally selected from zin...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L31/18H01L31/0392H01L31/09H01L31/101
CPCH01L31/1832H01L31/0392H01L31/03925H01L31/09H01L31/101Y02P70/50
Inventor 王丛刘铭高达周立庆
Owner 11TH RES INST OF CHINA ELECTRONICS TECH GROUP CORP