Wide-voltage SRAM time sequence tracking circuit
A timing tracking, wide voltage technology, applied in information storage, static memory, digital memory information and other directions, can solve the problems of increased delay variation, complex circuit structure, poor voltage tracking performance, etc.
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Embodiment 1
[0051] Example 1. The invention provides a wide-voltage SRAM timing tracking circuit, which is suitable for replicating a bit line discharge circuit. The timing tracking circuit includes a discharge switching module and a configurable SRAM timing logic module. In this preferred embodiment, the replica bit line discharge circuit adopts a traditional one-line replica bit line circuit, using 128bitcells / BL, without adding additional layout area, and the capacitance of the unilateral bit line is exactly the same as the traditional solution. figure 1 The circuit structures of the discharge switching module, the configurable SRAM sequential logic module and the replica bit line discharge circuit are shown. The in-line replicated bit line discharge circuit includes: 2K replicated bit line discharge cells (Replica Cell, RC) and J groups of redundant cells (Dummy Cell, DC). Each replicated bit line discharge cell RC has two input terminals and two output terminals. The first input ter...
Embodiment 2
[0057] Example 2. The circuit of the discharge switching model proposed by the present invention is as follows image 3 shown on the left.
[0058] The discharge switching module includes: a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMMOS transistor P6, a first NMOS transistor N1, and a second NMOS transistor tube N2, third NMOS tube N3, first inverter INV_1, second inverter INV_2, third inverter INV_3, fourth inverter INV_4, fifth inverter INV_5, sixth inverter INV_6 , a seventh inverter INV_7, a first NAND gate NAND_1, a first dynamic circuit, and a second dynamic circuit.
[0059] Further, the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, the fourth PMOS transistor P4, the fifth PMOS transistor P5, and the sixth PMOS transistor P6 are all P-type MOS transistors, and the first NMOS transistors N1, The second NMOS transistor N2 ...
Embodiment 3
[0075] Example 3. The circuit structure of the configurable SRAM sequential logic module proposed by the present invention is as follows: Figure 4 shown. The configurable SRAM sequential logic module uses the clock pulse CK output by the discharge switching module as the clock signal of the sequential logic module, and outputs the sense amplifier signal SAE and the word line signal WL. The configurable SRAM sequential logic module includes: a single pulse generation circuit and a pulse shift circuit. The single-pulse generating circuit uses the clock pulse CK as the clock signal of the circuit, and the output signal is the pulse signal PULSE, and the high-level pulse width of the pulse signal PULSE is consistent with the period of the clock pulse CK. The input signal of the pulse shift circuit is the pulse signal CK, and a pure shift register is used to generate and output the sense amplifier signal SAE and the word line signal WL.
[0076] The single pulse generating circ...
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