Three-dimensional chip packaging structure and packaging method

Abstract

The invention provides a three-dimensional chip packaging structure and a packaging method. The packaging structure comprises a packaging substrate; a three-dimensional stacked chip assembly which comprises a first chip assembly and a second chip assembly, wherein the size of the first chip assembly is larger than that of the second chip assembly; a thermal bridge structure formed on the first chip assembly, wherein a gap is formed between the thermal bridge structure and the second chip assembly; and a heat dissipation cover assembly formed on the packaging substrate, wherein the thermal bridge structure, the first chip assembly and the heat dissipation cover assembly are in thermal conduction. According to the invention, the heat bridge structure is introduced to form a heat conduction path, thereby facilitating the heat dissipation of the three-dimensional stacked chip, and greatly reducing the heat dissipation thermal resistance and temperature of the bottom chip. By means of the design, the temperature difference of the first chip can be reduced, and then thermal stress can be greatly reduced. The thermal bridge structure shares the pressure of a radiator and the like originally applied to the three-dimensional stacked chip, so that the packaging stress is more uniform, and the structure is more stable. The process is simple, and the existing packaging process flow and manufacturing process are not influenced basically.

Description

technical field [0001] The invention belongs to the technical field of semiconductor packaging, in particular to a three-dimensional chip packaging structure and packaging method. Background technique [0002] In the structure of three-dimensional stacked chips, different types of chips are often stacked together. However, the heat of the chips is difficult to dissipate, resulting in the failure of the stacked chips due to the high junction temperature, which limits the integration and performance of the entire device. improve. In addition, in the stacked chip, the upper chip is composed of multiple layers, each layer includes a micro-bump array interconnection form, and fills the underfill layer (underfill), resulting in a large thermal resistance from the bottom to the external heat dissipation cover, thus The temperature of the bottom chip is too high, and normal operation cannot be guaranteed. Some existing heat dissipation technologies have complex processes. Some tec...

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Problems solved by technology

[0004] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a three-dimensional chip packaging structure and packaging method, which are used to solve the problems in the prior art that the internal heat is difficult to dissipate and the temperature of the bottom chip is too high.

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