Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The forming method comprises the steps of providing a substrate, forming a gate structure on the substrate, forming source and drain doped layers in the substrate at the two sides of the gate structure, forming an etching stop layer covering the source and drain doped layers and the exposed side wall of the gate structure in a conformal mode on the substrate, and forming an interlayer dielectric layer on the substrate exposed out of the gate structure; forming contact holes in the interlayer dielectric layer and the etching stop layer at the two sides of the gate structure; etching the etching stop layer exposed out of the side wall of the contact hole along the direction vertical to the side wall of the contact hole to form a trench surrounded by the interlayer dielectric layer, the residual etching stop layer and the source-drain doped layer; and forming a contact hole plug for filling the groove and thecontact hole, wherein the contact hole plug is electrically connected with the source-drain doped layer. According to the embodiment of the invention, the contact resistance between the contact hole plug and the source-drain doped layer is reduced while the edge parasitic capacitance formed by the gate structure and the contact hole plug meets the process requirements.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background technique [0002] With the continuous development of integrated circuit manufacturing technology, people's requirements for the integration and performance of integrated circuits are becoming higher and higher. In order to improve integration and reduce costs, the critical dimensions of components are getting smaller and the circuit density inside integrated circuits is increasing. This development makes the surface of the wafer unable to provide enough area to make the required interconnection lines. [0003] In order to meet the requirements of the interconnection line after the critical dimension is reduced, at present, the conduction between different metal layers or between the metal layer and the substrate is realized through the interconnection structure. The inte...

AI Technical Summary

Problems solved by technology

In order to improve integration and reduce costs, the critical dimensions of components are continuously reduced, and the circuit density inside integrated circuits is increasing. This development makes the surface of the wafer unable to provide enough area to make the required interconnection lines.

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