Packaging crystal back grinding structure and grinding method

Abstract

The invention discloses a packaging wafer back grinding structure and a grinding method. The grinding method comprises the steps of preparing a glue; preparing a sample; taking a piece of cover glassand adhering the cover glass to an adhesive tape; dropwise adding the prepared glue on the cover glass, slowly putting the sample into the glue until the sample is completely immersed in the glue, lightly pressing the sample to discharge bubbles at the bottom of the sample, standing, observing whether bubbles are generated or not, puncturing the generated bubbles and then putting the sample on a heating table for baking so as to obtain the prepared sample; carrying out the post-treatment; after the sample is cooled, removing the adhesive tape, grinding off the redundant cover glass, adjustingthe cover glass to the proper size, and starting the packaging crystal back grinding. The packaging wafer back grinding structure is simple and is convenient in sample preparation, by the A and B gluepreparation, the stress on the sample is reduced, the flatness during grinding is kept, and the grinding area is increased. The packaging wafer back grinding structure has the advantages of high sample preparation success rate, better observation effect and the like.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a packaging crystal back grinding structure and a grinding method. Background technique [0002] Semiconductor chips often fail during research and development, mass production, and consumer use. With the rapid development of electronic science and technology and the continuous improvement of integration, semiconductor chips are becoming more and more complex, and people's requirements for product quality and reliability are constantly increasing. However, failure analysis technology is closely related to quality and reliability, which shows the importance of failure analysis technology. Through chip failure analysis, IC designers can help IC designers find design defects, process parameters that do not comply with regulations, or improper operation. [0003] In general, when performing hotspot positioning, some chips often choose to perform posit...

AI Technical Summary

Problems solved by technology

Smaller samples cannot be firmly adhered to the double-sided adhesive tape during crystal back grinding, and they tend to fall off during grinding, resulting in poor flatness and easy failure of crystal back grinding

In addition, when the CSP (Chip Scale Package, chip scale package) package sample is ground on the crystal back, due to the unevenness around the chip, the desired observation effect cannot be achieved.

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