Process method for inhibiting height asymmetry of metal gate

Abstract

The invention provides a process method for inhibiting height asymmetry of a metal gate. The process method comprises the following steps of providing a semiconductor structure of an NMOS region and aPMOS region which are isolated by an STI region, sequentially forming an interlayer dielectric layer, an HfO2 layer and a first TiN layer doped with magnesium ions on the semiconductor structure, removing the first TiN layer above the PMOS region, exposing the surface of the HfO2 layer above the PMOS region, and depositing a second TiN layer doped with aluminum ions, annealing the first TiN layerand the second TiN layer, so that magnesium ions in the first TiN layer diffuse into the HfO2 layer located above the NMOS region, and aluminum ions in the second TiN layer diffuse into the HfO2 layer located above the PMOS region, and removing the first TiN layer and the second TiN layer, so that the height of the HfO2 layer doped with the magnesium ions above the NMOS region is consistent withthe height of the HfO2 layer doped with the aluminum ions above the PMOS region. According to the method provided by the invention, the asymmetry of the height of the N / PMOS metal gates can be greatlyimproved. The method can be compatible with a traditional CMOS process and a DRAM process, the work function of the metal gate can be accurately regulated and controlled, and therefore the process window of the CMOS is increased.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a process method for suppressing height asymmetry of metal gates. Background technique [0002] With the continuous scaling of semiconductor circuits, DRAM peripheral circuit transistors have gradually changed from polysilicon / SiO2 structures to High-k metal gates. Especially with the rapid development of the Internet of Things, the demand for low-power mobile devices is becoming more and more extensive, and the requirements for device leakage are also increasing. The gate leakage and junction leakage requirements of transistors in peripheral circuits of storage cells are generally higher than those of logic regions, so as to achieve better off-state current control. Therefore, a high-k metal gate (high-k metal gate) process with better performance and lower power consumption has become the best choice for DRAM peripheral circuits. An extremely important issue in the Hig...

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Problems solved by technology

[0003] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a process method for suppressing the height asymmetry of the metal gate, which is used to solve the work function drift caused by high temperature annealing and the gate height of NMOS and PMOS in the prior art Different problems that lead to difficulties in the subsequent process flow

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