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Semiconductor structure and forming method thereof

一种半导体、图形结构的技术,应用在半导体器件、半导体/固态器件制造、电固体器件等方向,能够解决性能有待提升等问题

Pending Publication Date: 2020-10-27
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The performance of the fin field effect transistor formed by the existing technology needs to be improved

Method used

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  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0027] As mentioned in the background, the performance of the fin field effect transistor formed by the prior art needs to be improved. The structure of a fin field effect transistor is now described and analyzed.

[0028] Figure 1 to Figure 3 It is a schematic cross-sectional structure diagram of a formation process of an embodiment of a semiconductor structure.

[0029] Please refer to figure 1 , providing a base 100 with fins 101 on the base, and the fins 101 are separated from each other on the substrate 100 .

[0030] Please refer to figure 2 A mask layer 102 is formed on the substrate 100 and the fins 101 , the mask layer 102 exposes part of the fins 101 ; part of the fins 101 is removed to form a target fin 103 .

[0031] Please refer to image 3 After the target fin 103 is formed, the mask layer 102 is removed, and an isolation structure 104 is formed on the substrate 100 , the isolation structure 104 covers part of the sidewall of the target fin 103 and is lowe...

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PUM

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Abstract

The invention provides a semiconductor structure and a forming method thereof. The method comprises: providing a substrate, wherein the substrate comprising a first region, a plurality of second regions and a plurality of third regions, the first region is located between two adjacent third regions, two sides of the first region are respectively provided with one second region, and each second region is located between the first region and the third region; forming a pattern structure on the substrate, wherein the pattern structure comprises a first pattern layer located on the first region, asecond pattern layer located on the second region and a third pattern layer located on the third region, the first pattern layer and the second pattern layer are discrete from each other, and the second pattern layer and the third pattern layer are discrete from each other; removing the second pattern layer; and after the second pattern layer is removed, etching the substrate by taking the firstpattern layer and the third pattern layer as masks to form a base, a first fin part located on the base and a second fin part located on the base, wherein the first fin part is formed by etching by taking the first pattern layer as a mask, and the third fin part is formed by etching by taking the third pattern layer as a mask. According to the invention, the performance of the formed semiconductorstructure is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] In the field of semiconductor technology, transistors, as the most basic semiconductor devices, are currently being widely used. Fin field effect transistor is a new complementary metal oxide semiconductor (CMOS) transistor, which can improve circuit control and reduce leakage current, shorten the gate length of transistor, can greatly improve chip processing speed and greatly reduce power consumption, It has been widely used in the circuits of various semiconductor devices. [0003] As the manufacturing of integrated circuits develops towards ultra-large-scale integrated circuits, the internal circuit density is getting larger and larger. With the reduction of technology nodes, the size of the formed semiconductor structure is getting smaller and smaller, forming fin field effect tra...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L29/78
CPCH01L29/66795H01L29/785H01L21/823481H01L21/823431H01L27/0886H01L21/3086H01L21/3088H01L21/823412H01L21/823418H01L21/3085H01L29/0847H01L21/3081
Inventor 王楠
Owner SEMICON MFG INT (SHANGHAI) CORP
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