Semiconductor package structure and manufacturing method thereof
A technology of packaging structure and manufacturing method, applied in the direction of semiconductor/solid-state device manufacturing, semiconductor device, semiconductor/solid-state device components, etc., can solve the problem that plane process and manufacturing technology cannot meet the growing and changing needs of semiconductor devices, etc. Achieve the effect of reducing delay, improving overall performance, and shortening distance
Active Publication Date: 2021-06-04
YANGTZE MEMORY TECH CO LTD
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Problems solved by technology
[0003] With the continuous reduction of the feature size of semiconductor devices and the continuous increase of storage capacity, planar technology and manufacturing technology can no longer meet the growing and changing needs of semiconductor devices
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[0035] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.
[0036] In the following description, many specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways than those described here, so the present invention is not limited by the specific embodiments disclosed below.
[0037] As indicated in this application and claims, the terms "a", "an", "an" and / or "the" do not refer to the singular and may include the plural unless the context clearly indicates an exception. Generally speaking, the terms "comprising" and "comprising" only suggest the inclusion of clearly identified steps and elements, and these steps and elements do not constitute an exclusive list, and the method or device may also contain other st...
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The present invention relates to a semiconductor packaging structure and a manufacturing method thereof. The manufacturing method includes: providing a first wafer; cutting the first wafer to obtain a plurality of chips to be packaged, each of which includes a variety of dies , the sizes of the plurality of dies are different; the plurality of chips to be packaged are tested to obtain known qualified chips that pass the test; a second wafer is provided, and the second wafer includes a plurality of controller circuit dies; and hybrid bonding the known qualified chip and the controller circuit die. The invention improves the overall performance of the semiconductor device and the qualified rate of products by bonding the memory devices with different sizes and functions to the controller circuit chip.
Description
technical field [0001] The invention relates to the field of semiconductors, in particular to a semiconductor packaging structure and a manufacturing method thereof. Background technique [0002] Semiconductor packaging refers to the process of processing the tested wafers into independent chips according to the product model and functional requirements. In the packaging process, the wafer is cut into small dies (Die) after the dicing process, and then the cut dies are mounted on the small islands of the corresponding substrate (lead frame) frame, and then the ultra-fine The metal wire or conductive resin connects the chip's bonding pad (Bonding Pad) to the corresponding pin of the substrate to form the required circuit, and then the independent die is packaged and protected with a plastic shell. [0003] With the continuous reduction of the feature size of semiconductor devices and the continuous increase of storage capacity, the planar process and manufacturing technology...
Claims
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IPC IPC(8): H01L21/50H01L23/48H01L27/108H01L27/11H01L27/11524H01L27/11551H01L27/1157H01L27/11578H10B10/00H10B12/00H10B41/20H10B41/35H10B43/20H10B43/35
CPCH01L21/50H01L23/48H01L24/80H01L2224/80001H10B12/00H10B10/00H10B41/35H10B41/20H10B43/35H10B43/20H01L2224/73265H01L2224/48227H01L2224/32145H01L2924/15311H01L2224/08145H01L2924/00
Inventor 刘峻程卫华肖莉红
Owner YANGTZE MEMORY TECH CO LTD