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Method for preparing magnetic tunnel junction cell array

A technology of magnetic tunnel junction and cell array, which is applied to the manufacture/processing of magnetic field controlled resistors and electromagnetic devices, and can solve the problems that the surface flatness cannot be achieved.

Pending Publication Date: 2020-12-15
SHANGHAI CIYU INFORMATION TECH
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Problems solved by technology

However, when performing Chemical Mechanical Polarization (CMP) on patterned CMOS vias, due to the existence of butterfly defects (Disshing), the surface flatness does not reach the level of making magnetic tunnel junctions ( MTJ) requirements

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  • Method for preparing magnetic tunnel junction cell array
  • Method for preparing magnetic tunnel junction cell array
  • Method for preparing magnetic tunnel junction cell array

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Embodiment Construction

[0025] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0026] see Figure 1-8 , the present invention provides a technical solution: a method for preparing a magnetic tunnel junction cell array, comprising a CMOS substrate 1, a metal wiring Mx (x≥1) interlayer dielectric 101, a metal wiring Mx (x≥1) 102, BEV etch barrier 2, BEV interlayer dielectric 3, BEV after etch 4, BEV metal diffusion barrier 5, BEV and BE deposited metal 6, BEV metal fill 7, BE metal 8, magnetic tunnel junction (MTJ) buffer / s...

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Abstract

The invention relates to a method for preparing a magnetic tunnel junction unit array. The method for preparing the magnetic tunnel junction unit array comprises the following specific steps of 1, providing a CMOS substrate with a polished surface and a metal connection line Mx; 2, manufacturing an etched bottom electrode through hole on the planarized CMOS substrate; 3, BEV and BE deposited metalbeing deposited to form BEV metal filling and BE metal, and the BE metal being subjected to planarization treatment to meet the requirement for MTJ multilayer film deposition; and 4, depositing a magnetic tunnel junction and a top electrode on the flattened BE metal, graphically defining a magnetic tunnel junction pattern, etching the top electrode, the magnetic tunnel junction and the BE metal,and depositing an insulating covering layer around the etched top electrode, magnetic tunnel junction and BE metal.

Description

technical field [0001] The invention relates to the technical field of magnetic random access memory (MRAM, Magnetic Radom Access Memory), in particular to a method for preparing a magnetic tunnel junction unit array. Background technique [0002] In recent years, MRAM using Magnetic Tunnel Junction (MTJ) is considered to be the future solid-state non-volatile memory, which has the characteristics of high-speed reading and writing, large capacity and low energy consumption. Ferromagnetic MTJ is usually a sandwich structure, which has a magnetic memory layer, which can change the magnetization direction to record different data; an insulating tunnel barrier layer in the middle; a magnetic reference layer, located on the other side of the tunnel barrier layer, which The direction of magnetization remains unchanged. [0003] In order to record information in this magnetoresistive element, it is suggested to use a writing method based on spin-momentum transfer or spin transfer ...

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Application Information

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IPC IPC(8): H01L43/12H01L43/08
CPCH10N50/01H10N50/10
Inventor 张云森郭一民肖荣福陈峻
Owner SHANGHAI CIYU INFORMATION TECH
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