DDR control system and DDR storage system

Abstract

The invention provides a DDR (Double Data Rate) control system and a DDR storage system, based on an SoC (System on Chip) framework consisting of an MCU (Microprogrammed Control Unit) kernel and an FPGA (Field Programmable Gate Array) kernel integrated in the same system on chip, the DDR control system between the MCU and an off-chip DDR memory is realized on the basis of logic resources in the FPGA kernel, and the DDR control system is an on-chip DDR control system. The system comprises an MCU bus mapping module, a DDR data cache module and a DDR controller module, the number of the DDR controller modules and the number of subsystem buses mapped by the MCU bus mapping module can be dynamically adjusted on the basis of the programmable characteristic of an FPGA, a user can dynamically configure the number of the DDR controller modules outside an MCU, and furthermore, the accessed off-chip DDR memory is dynamically configured through the DDR controller module, so that the purpose of dynamically configuring the functions and data of the off-chip DDR memory is achieved, the expansibility and usability of the MCU are improved, and a user can quickly apply the DDR memory.

Description

Technical field[0001]The present invention relates to the field of DDR storage technology, in particular to a DDR control system and a DDR storage system.Background technique[0002]Compared with traditional single data rate memory, Double Data Rate (DDR) memory technology realizes two read and write operations in one clock cycle, that is, they are executed on the rising and falling edges of the clock. One read and write operation. The speed advantage of DDR memory is widely used in image processing and other fields.[0003]With the rapid development of DDR memory technology, higher requirements are put forward in the field of microcontroller (Micro Controller Unit, MCU) control, especially in the field of image processing, where the MCU is required to directly access the DDR memory. However, there is no dedicated DDR interface in the traditional MCU single-core architecture. When the MCU core accesses its external DDR memory, it also needs to be implemented through an off-chip DDR cont...

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to provide a kind of DDR control system and DDR storage system, can realize the DDR control system on-chip based on FPGA logic resource, to solve the problem that traditional MCU must rely on external DDR control chip to read and write control DDR memory problem

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