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Multi-channel DAC sampling synchronization system

A sampling synchronization, multi-channel technology, applied in the direction of digital-to-analog converters, etc., can solve the problem that the DAC cannot meet the high sampling and synchronous multi-source output, etc., to achieve the effect of high controlled synchronization ability, avoid synchronization errors, and simple hardware structure

Active Publication Date: 2021-01-05
10TH RES INST OF CETC
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  • Abstract
  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to propose a simple hardware structure, high synchronization control ability, strong scalability, and can meet the requirements of high sampling and multi-channel DAC sampling synchronization for the existing DAC.

Method used

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Embodiment Construction

[0015] refer to figure 1 . In the preferred embodiment described below, a multi-channel DAC sampling synchronization system includes: a large-scale programmable gate array FPGA connected to an external clock source and a clock distribution chip, and the FPGA chip is connected in parallel to a multi-channel high-speed digital-to-analog converter DAC. The FPGA chip built-in program software integrates a clock configuration module, a digital signal source generation module, a DAC configuration module and a JESD204B configuration module; the external clock source inputs the clock source data flow into the clock configuration module, the DAC configuration module and the clock distribution chip respectively , provide the logic clock for the clock configuration module and the DAC configuration module respectively, and provide the reference clock for the clock distribution chip; the clock configuration module completes the specific parameter configuration for the multi-channel clock ...

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Abstract

The invention discloses a multi-channel DAC sampling synchronization system, and belongs to the technical field of high-speed serial interface chips. The invention aims to provide a DAC synchronization system capable of meeting high-speed sampling. The system is realized through the following technical scheme: a clock source and an FPGA loading program are externally provided, a digital signal source generation module generates a digital signal source according to a logic clock provided by a clock distribution chip, the digital signal source is sent to a JESD204B configuration module, multi-channel data framing and packaging are performed according to information such as the number of channels of a DAC chip and the number of DAC converters, and an IP core is called to extract frame data and the frame data is mapped into effective coded words, high-speed serial data required by each DAC converter is formed by adopting different sorting modes, frames of control characters in a high-speedserial data stream is aligned by the DAC chip according to configuration, frame decoding is completed according to the requirements of a JESD204B protocol and the frames are output to multiple channels, thereby realizing high-speed DAC sampling multi-channel synchronization.

Description

technical field [0001] The invention belongs to the technical field of high-speed serial interface chips, and relates to an FPGA homologous data and multi-channel DAC sampling synchronization system based on the JESD204B protocol. [0002] technical background [0003] Parallel interfaces have been gradually replaced by high-speed serial interfaces as the data throughput requirements become higher and higher. The high-speed serial / deserializer interface specification (JESD204B protocol) supports a data transmission rate of up to 12.5Gbyte / s, has the characteristics of a small number of pins and high scalability, and has become the mainstream standard for the interface of digital-analog / analog-digital conversion devices. Since a single-channel DA chip cannot meet the requirements of high sampling and multi-source output, a common method is to use a multi-channel digital-analog DA chip to synchronously output signals to increase the sampling rate and increase the number of outp...

Claims

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Application Information

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IPC IPC(8): H03M1/66
CPCH03M1/66
Inventor 胡洪唐洪军张晓波张艳如
Owner 10TH RES INST OF CETC
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