Method for forming source-drain region epitaxial layer of semiconductor device, and semiconductor device

Abstract

The invention relates to a method for forming a source-drain region epitaxial layer of a semiconductor device, and relates to a semiconductor integrated circuit manufacturing technology. The method comprises the following steps of: forming an epitaxial layer through an epitaxial process to fill a groove, then adding a photoetching process to etch off the redundant epitaxial layer in the groove, enabling the residual epitaxial layer to form the first epitaxial layer of the embedded epitaxial layer of a source-drain region, and enabling the first epitaxial layer to completely cover the inner wall of the groove, so that the subsequently formed second epitaxial layer is completely separated from the channel, doping elements in the second epitaxial layer are prevented from diffusing into the channel in the subsequent process, the leakage current is reduced, and the device performance is improved.

Description

technical field [0001] The invention relates to the manufacturing technology of semiconductor integrated circuits, in particular to a method for forming epitaxial layers in source and drain regions of semiconductor devices. Background technique [0002] With the development of technology, the critical dimension (CD) of the device is getting smaller and smaller. When the process node of the device is below 28nm, it is often necessary to use embedded epitaxial layers in the source and drain regions to change the stress of the channel region, thereby increasing the current carrying capacity. Mobility of electrons and thus improve the performance of the device. For PMOS devices, the embedded epitaxial layer usually adopts silicon germanium epitaxial layer (SiGe); for NMOS devices, the embedded epitaxial layer usually adopts phosphorus silicon epitaxial layer (SiP). [0003] Usually, after the gate structure of the device is formed, grooves are formed on both sides of the gate s...

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Problems solved by technology

However, a small distance from the groove 120 to the channel will result in poor step coverage of the epitaxially grown first epitaxial layer 10, such as Figure 1b As shown by the number 13 in the above, the groove 120 is not completely covered by the first epitaxial layer 10, and the second epitaxial layer 11 will be directly in contact with the channel during the subsequent epitaxial growth process, while the second epitaxial layer 11 The doping concentration of the epitaxial layer is much higher than that of the first epitaxial layer 10. During the subsequent annealing process, the dopant elements will diffuse into the channel, resulting in an increase in the leakage current, which seriously affects the performance of the device. Reducing the leakage current is the current advanced technology such as 14nm The key bottleneck of devices based on high dielectric material metal gate fin field effect transistors

At present, it is difficult to make the first epitaxial layer completely cover the sidewall of the groove only by optimizing the epitaxial growth process

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