Compiling method for reducing multi-class memory access conflicts for coarse-grained reconfigurable structure

Abstract

The invention relates to a compiling method for reducing multi-class memory access conflicts for a coarse-grained reconfigurable structure, which comprises the steps that when the rear end face of a compiler is high, a memory access pressure allocation method is adopted for processing, the starting time of different sub DFGs is adjusted, and a scheduling result is processed through an array initial address offset allocation method; according to the method, different array initial addresses accessed by all memory access operations within a period of time are adjusted, processing of a conflict perception mapping method is further included, different operations are mapped to a PE according to a conflict matrix and the current mapping situation, and the correctness of the mapping process is ensured through a reordering and backtracking algorithm. The method has the beneficial effects that multi-memory-bank conflicts among multiple groups are effectively reduced, and the time cost of a mainmemory for transmitting data to an on-chip memory by utilizing DMA is greatly reduced; higher application speed-up ratio on CGRA is avoided due to memory access conflict; the compiler rear-end process is simple in structure, low in algorithm complexity and high in compiling speed.

Description

technical field [0001] The invention relates to the field of a coarse-grained reconfigurable structure compiler, in particular to a data partition and operator mapping method for reducing multi-storage bank conflicts and interconnection conflicts in a coarse-grained reconfigurable structure. Background technique [0002] With the development of microelectronics technology, Moore's Law is gradually coming to an end, and it is difficult to further improve the main frequency of microprocessors. Coarse-Grained Reconfigurable Architecture (CGRA) is an architecture that can achieve higher energy efficiency than traditional architectures in the post-Moore's Law era. Coarse-grained reconfigurable architectures are often applied to accelerate computationally intensive applications. In modern real-life applications, application execution time is mostly consumed at a small number of loop cores. Therefore, optimization for mapping loop kernels to reconfigurable architectures is of gre...

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Problems solved by technology

Second, the delay caused by memory access conflicts between memory access operations in the same control cycle (Control Step, CS) accounts for 68.4% of the total running time

[0008] However, there are three problems in the above research: First, the above research is all about how to reduce multi-bank conflicts, but they all ignore the performance loss caused by interconnection conflicts. The kernel will greatly reduce the performance; second, the above-mentioned strategies for solving multi-bank conflicts can only solve the situation that the distance between the two memory access operations is constant during the entire operation process, and it is not suitable for the relationship between memory access operations. The situation changes with the progress of the loop iteration; the third is that the above research uses a complex linear transformation data placement strategy to solve multi-bank conflicts, which brings about an increase in the complexity of data storage in the on-chip memory, which will cause the main memory to use the direct memory. The time cost of accessing (Direct Memory Access, DMA) to transfer data to the on-chip memory is increased, which in turn leads to a reduction in the application acceleration ratio of the reconfigurable processor

However, most of the above studies do not consider the impact of memory access conflicts on performance, and a few scheduling schemes that consider memory access conflicts only consider multi-bank conflicts, but do not consider interconnection conflicts.

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