A compilation method for reducing multi-class memory access conflicts for coarse-grained reconfigurable structures

Abstract

A compilation method for reducing multi-type memory access conflicts for coarse-grained reconfigurable structures. When the height of the rear end of the compiler is high, the memory access pressure allocation method is used for processing, and the startup time of different sub-DFGs is adjusted. The scheduling results will be passed through the array The start address offset allocation method is used to adjust the start addresses of different arrays accessed by all memory access operations within a period of time, and also includes the processing of conflict-aware mapping methods, which map different operations to PEs according to the conflict matrix and current mapping conditions Above, the reordering and backtracking algorithms ensure the correctness of the mapping process. The beneficial effects of the present invention are as follows: effectively reduce multi-storage bank conflicts between multiple groups, greatly reduce the time cost of transferring data from the main memory to the on-chip memory by using DMA; avoid memory access conflicts, and bring higher application acceleration ratios on CGRA; The back-end process of the compiler has a simple structure, low algorithm complexity, and fast compilation speed.

Description

technical field [0001] The present invention relates to the field of coarse-grained reconfigurable structure compilers, in particular to a data partition and operator mapping method for reducing multi-memory bank conflicts and interconnection conflicts in coarse-grained reconfigurable structures. Background technique [0002] With the development of microelectronics technology, Moore's Law is gradually coming to an end, and it is difficult to further improve the frequency of microprocessors. Coarse-Grained Reconfigurable Architecture (CGRA) is an architecture that can achieve higher energy efficiency than traditional architectures in the post-Moore's Law era. Coarse-grained reconfigurable architectures are often used to accelerate computationally intensive applications. In modern real life applications, application execution time is mostly consumed at a small number of loop cores. Therefore, optimizing the mapping of loop kernels to reconfigurable architectures is of great...

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Problems solved by technology

Second, the delay caused by memory access conflicts between memory access operations in the same control cycle (Control Step, CS) accounts for 68.4% of the total running time

[0008] However, there are three problems in the above research: First, the above research is all about how to reduce multi-bank conflicts, but they all ignore the performance loss caused by interconnection conflicts. The kernel will greatly reduce the performance; second, the above-mentioned strategies for solving multi-bank conflicts can only solve the situation that the distance between the two memory access operations is constant during the entire operation process, and it is not suitable for the relationship between memory access operations. The situation changes with the progress of the loop iteration; the third is that the above research uses a complex linear transformation data placement strategy to solve multi-bank conflicts, which brings about an increase in the complexity of data storage in the on-chip memory, which will cause the main memory to use the direct memory. The time cost of accessing (Direct Memory Access, DMA) to transfer data to the on-chip memory is increased, which in turn leads to a reduction in the application acceleration ratio of the reconfigurable processor

However, most of the above studies do not consider the impact of memory access conflicts on performance, and a few scheduling schemes that consider memory access conflicts only consider multi-bank conflicts, but do not consider interconnection conflicts.

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