35results about How to "Compile fast" patented technology

The invention discloses a Gerber file compiler based on regular expressions, and relates to the technical field of high-level language compilation or explanation. The Gerber file compiler comprises an architecture part and an algorithm implementation part, wherein the architecture part comprises a compilation application module and a compilation application support module, and call between the compilation application module and the compilation application support module is achieved through an API; according to algorithm implementation, a Gerber file is described in a formalized mode through three-type grammar, then the regular expressions are used for building corresponding rule lists for lexical analysis and grammatical analysis, according to the rule lists, lexical analysis and grammatical analysis threads are executed in a compiling mode, image information matching is performed at the same time, and matching results are stored through two-way linked lists. The compiler is used for compiling the Gerber file and has the advantages of being high in generality and compiling efficiency.

The invention relates to a construction and compiling method and device of an operating system, electronic equipment and a storage medium. The method comprises: obtaining a corresponding system compiling tool in a compiling environment in response to a compiling instruction; calling a system compiling tool, collecting a tool chain of the first operating system and a corresponding basic code library, and constructing a root system of the first operating system; scanning a basic code layer of the second operating system, selecting a corresponding compiler for the basic code layer according to the compiling rule, and generating a fusion compiling framework; determining a dependency relationship between framework layers contained in a compiling framework, generating a dependency tree sorted according to compiling priorities according to the dependency relationship, and representing compiling modules of the framework layers by nodes in the dependency tree; and according to the dependency relationship in the dependency tree, calling a compiling module of the framework layer to obtain a compiling source code, installing the framework layer into the root system, and generating a compiling file system. The system compiling efficiency is greatly improved.

The invention discloses implementation of a novel compiling method and compiler of a regular expression hardware circuit on the basis of an NFA (Nondeterministic finite automaton). Under a compiler frame, a full-automatic compiling process is realized, and through seven program segments, each component of each program segment is realized and can be connected according to an integral functional frame. The invention puts forward a novel regular expression hardware circuit conversion method, a traditional MY ((McNaughton-Yamada) construction algorithm is improved, and chained analysis is adopted to replace deep tree analysis so as to reduce repeated depth. A novel NFA state recording structure is defined, and matching and negative matching functions are compatible. Conversion, simulation, testing and synthesis processes from the regular expression to the hardware circuit are realized. The above method can be synthesized to quickly and efficiently finish automatic compiling from the regular expression to RTL (Real Time Logistics), and the configuration of large-scale regular matching engines can be quickly and automatically finished.

The invention discloses a vector modulating signal processing method and a vector modulating signal processing device. The method comprises the steps of setting a signal processing unit and a configuration unit on an FPGA (Field Programmable Gate Array), setting configuration parameters through the configuration unit, carrying out pulse shaping, filtering noise reduction and the like on data sent to the FPGA according to the configuration parameters in the configuration unit, performing up-conversion on the processed large-scale data with low sampling rate through any interpolating decimation rate to some small-range data with high sampling rate, and transmitting to a DAC (Digital-to-Analog Converter) chip, thereby greatly improving the precision and purity of a baseband signal.

The invention provides a visualized robot program compiling method. The method includes that (1) a servo control system is adopted to unlock a servo motor for controlling joints of a robot, programming personnel directly adjust the joints of the robot from initial positions to a required position state, and then the servo control system locks the servo motor again; and (2) the servo control system is adopted to detect pulse information of the servo motor when the servo motor passively rotates in the moving process of the joints, and then transmits the pulse information to a program compiling system, and the program compiling system converts the pulse information into corresponding data of position changes of the joints of the robot. The data of the position changes of the joints are used as program data of movement control of the joints of the robot. Through adoption of the visualized robot program compiling method, the joints of the robot can be directly adjusted. The data of the position changes of the joints can be obtained through the servo motor of the joints and the servo control system for controlling the servo motor and then converted into the program data through the program compiling system. The visualized robot program compiling method greatly reduces the difficulty in robot program compiling, eliminates branch circulation, judgment and other logic processes in a former program, reduces complexity of the program, and enables the program compiling to be simpler, more convenient and faster.

The embodiment of the invention discloses a distributed compiling method and system, a main server and a storage medium. The method is applied to a main server deployed with an engine editor and a distributed compiling module, and comprises the steps that after the engine editor receives a compiling task, a starting task and starting parameters corresponding to the compiling task are sent to the distributed compiling module; the distributed compiling module determines a working server from candidate servers which can be in communication connection with the engine editor in a target network according to the received starting task, starts a working compiler deployed on the working server, transmits received starting parameters to the working compiler in an unvarnished manner, and sends the starting parameters to the working compiler; the work compiler is connected to the engine editor according to the starting parameters; and the engine editor sends the compiling task to the work compiler which is successfully connected to the engine editor, so that the work compiler compiles according to the received compiling task. According to the technical scheme, the compiling speed can be increased.

The invention relates to a compiling method for reducing multi-class memory access conflicts for a coarse-grained reconfigurable structure, which comprises the steps that when the rear end face of a compiler is high, a memory access pressure allocation method is adopted for processing, the starting time of different sub DFGs is adjusted, and a scheduling result is processed through an array initial address offset allocation method; according to the method, different array initial addresses accessed by all memory access operations within a period of time are adjusted, processing of a conflict perception mapping method is further included, different operations are mapped to a PE according to a conflict matrix and the current mapping situation, and the correctness of the mapping process is ensured through a reordering and backtracking algorithm. The method has the beneficial effects that multi-memory-bank conflicts among multiple groups are effectively reduced, and the time cost of a mainmemory for transmitting data to an on-chip memory by utilizing DMA is greatly reduced; higher application speed-up ratio on CGRA is avoided due to memory access conflict; the compiler rear-end process is simple in structure, low in algorithm complexity and high in compiling speed.

The invention relates to a cross-platform multi-language compiling method and an ultra-light Internet-of-Things virtual machine. The method comprises the following steps: converting a source code formed by a high-level programming language into an intermediate code in a preset format through a general grammar front-end parser; compiling the intermediate code into a byte code in a preset format through a compiler; and judging whether the loading is cross-language loading or not, loading and executing the intermediate code in the preset format or the byte code in the preset format in combination with target loading time, and outputting an execution result. According to the method, a set of standard and extensible byte code formats are executed by using the ultra-light Internet-of-Things virtual machine, so grammatical characteristics of different programming languages can be met, multi-language mixed development is performed, a compiling volume and occupied memory are reduced by translating different languages into more abstract intermediate codes, and the virtual machine can be conveniently used on a miniaturized Internet-of-Things terminal.

The invention discloses a feature rule matching library updating method, a feature rule matching library updating device, a storage medium and electronic equipment. The method comprises the followingsteps: receiving a feature rule processing instruction which comprises a feature rule processing type and feature rule information; determining a target sub-library according to the feature rule processing instruction, and updating the target sub-library based on the feature rule processing type and the feature rule information; determining a target sub-library updated in a preset time interval according to the preset time interval; and compiling the updated target sub-library, and updating a feature rule matching library according to the compiled feature rule matching sub-library. The space for storing the feature rules is divided into the multiple independent sub-libraries, the sub-libraries are small in capacity and high in compiling speed, the sub-libraries are independent of one another and can be compiled in parallel, compiling time is shortened, compiling efficiency of the feature rule matching library is improved, and compiling real-time performance of the feature rule matchinglibrary is improved.

The invention provides a Hadoop compiling method and device and a computer readable storage medium, belongs to the technical field of big data processing systems, and solves the problems that in the prior art, an open source community does not adapt to Hadoop, and generally native Hadoop is of an x86 architecture, so that Hadoop cannot be directly used on a non-x86 machine, and if the Hadoop needsto be used on the non-x86 machine, the recompilation must be carried out. The method comprises the steps of detecting and identifying a current processor architecture and an operating system; obtaining a compiling environment according to the processor architecture and the operating system; pulling a dependence package required by compiling from a local warehouse; performing Hadoop compiling based on the dependency package, and obtaining the compiling environment according to the processor architecture and the operating system, wherein the method comprises the steps that the compiling environment needed by the processor architecture and the operating system is determined; and judging whether the current environment meets a compiling environment or not, and if not, building the compiling environment by utilizing the script until a processor architecture and an operating system are met.