Synchronous reset pulse output pixel structure for realizing correlated double sampling
A technology of correlated double sampling and reset pulse, which is applied in the direction of image communication, color TV parts, TV system parts, etc. It can solve the problems of high noise in the fixed mode and the inability to perform double sampling of pixels, so as to reduce the amount of data , reduce pixel FPN, reduce the effect of pixel area
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[0012] In order to make the purpose, technical solutions and advantages of the present invention more clear, the following will give a specific description of the implementation of the present invention in conjunction with examples.
[0013] The present invention proposes a synchronous reset pulse output pixel structure that realizes correlated double sampling, stores the input offset voltage of the op amp by connecting the op amp into a closed-loop mode before integration, and delays the timing operation of the feedback switch being turned off by the reset switch Further realize reset noise storage and reset tube charge injection storage. The key to the pixel control logic is to generate control signals S1, S2, and S3 that are delayed in response to Sr; this delay can be achieved by introducing an additional clock signal that is delayed in Read, or through an inverter in the pixel. A pixel control logic circuit that generates a control signal delay through a pixel inverter su...
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