40results about How to "Reduce pixel area" patented technology

A display device is disclosed. The display device includes: a pixel array unit and a driving unit which drives the pixel array unit. The pixel array unit includes rows of scanning line, columns of signal lines, pixels in a matrix state arranged at portions where scanning lines and signal lines cross each other and power supply lines arranged corresponding to respective rows of pixels. The driving unit includes a main scanner performing line-sequential scanning to pixels by each row by supplying a control signal to each scanning line sequentially, a power supply scanner supplying a power supply voltage which is switched to a first potential and a second potential to each power supply line so as to correspond to the line-sequential scanning, and a signal selector supplying a signal potential and a reference potential to be video signal to columns of signal lines so as to correspond to the line-sequential scanning.

A display device includes a pixel array unit and a driver unit. A sampling transistor samples a signal potential to hold the signal potential in a holding capacitor. A driver transistor flows a drive current to a light emitting element in accordance with the signal potential held. A power supply scanner in the driver unit changes a power supply line from a first potential to a second potential before the sampling transistor samples the signal potential. A main scanner in the driver unit makes the sampling transistor conductive to apply a reference potential from the signal line to the gate of the driver transistor and to set the source of the driver transistor to a second potential. The power supply scanner changes the power supply line from the second potential to the first potential to hold a voltage corresponding to a threshold voltage off the driver transistor in the holding capacitor.

A pixel circuit, a display device, and a method of driving a pixel circuit able to obtain a source-follower output without luminance deterioration even when the current-voltage characteristic of a light emitting element changes due to aging, making a source-follower circuit of n-channel transistors possible, and in addition able to display uniform and high quality images not without regard to variations of threshold values and mobilities of the active elements inside pixels, wherein a capacitor C111 is connected between a gate and a source of a TFT 111, the source side of the TFT 111 is connected to a fixed potential (GND) through a TFT 114, a predetermined reference current Iref is supplied to the source of the TFT 111 with a predetermined timing, a voltage corresponding to the reference current Iref is held, and an input signal voltage centered about the voltage is coupled, whereby an EL light emitting element 19 is driven centered about the center value of variation of the mobilities.

According to the embodiment, the invention discloses a deformed display panel and a display device. A marginal display area of the deformed display panel comprises at least one curved display boundary; the marginal display area comprises at least one first type of pixel units; the first type of pixel units comprise a first margin and a second margin; the first margin is represented as a curve; the first type of pixel units at least include a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit; the green sub-pixel unit, the green sub-pixel unit and the blue sub-pixel unit are identical in pixel area; or the green sub-pixel unit is greater than the red sub-pixel unit and the blue sub-pixel unit in pixel area. In conclusion, the first margin of the first type of pixel units, which is represented as the curve, is matched with the curved display boundary, so that a good marginal display effect of the deformed display panel is guaranteed; by arranging the three sub-pixels which are identical in area, display color is guaranteed; and by virtue of the green sub-pixel which is relatively large in area, display brightness is guaranteed.

The invention provides a display device and a driving method thereof, relating to the technical field of display, and solving the problem that high resolution ratio of the conventional display panel is difficultly realized. The display device comprises a display panel, a first driver module, a second driver module, and an optical modulator positioned on the light emergent side of the display panel; multiple prism structures are formed between the display panel and the optical modulator; the pixels comprise n virtual pixels; the optical modulation unit comprises n optical modulation areas which correspond to the virtual pixels; a frame picture comprises n sub-frame pictures; the first driver module is used for driving the display panel to sequentially display n continuous sub-frame pictures in the frame picture; the second driver module is used for driving the n optical modulation areas of the optical modulation unit to be sequentially light-transmitting areas in the n sub-frame pictures, and other (n-1) optical modulation areas are shading areas. Moreover, the optical modulator reflects one part of light rays in the shading areas to enter the prism structures, so that the one part of light rays can be emitted from the light-transmitting areas.

Disclosed herein is a display apparatus including: a pixel array; and a driver configured to drive the pixel array. The pixel array including rows of scanning lines, columns of signal lines, a matrix of pixels disposed at crossings of the scanning lines and the signal lines, and feeding lines associated with respective rows of the pixels, the pixels including respective sampling transistors having respective gates connected to the scanning lines, the driver including a main scanner configured to supply control signals to the scanning lines, the main scanner including a shift register, output buffers connected respectively between the shift register and the scanning lines, and a pulse power supply configured to supply power supply pulses, each having a predetermined pulse duration, to the output buffers, wherein the main scanner outputs power supply pulses supplied from the pulse power supply as the control signals to the respective scanning lines in response to a shift pulse output from the shift register.

Disclosed is a flat panel display capable of enhancing a white balance by making a doping concentration or shape and size of drain offset regions of driving transistors different, in R, G and B unit pixels of each pixel. A flat panel display, comprises a plurality of pixels, where each of pixels including R, G and B unit pixels to embody red (R), green (G) and blue (B) colors, respectively. Each of the unit pixels includes a transistor with source/drain regions. Transistors of at least two unit pixels of the R, G and B unit pixels have drain regions of different geometric structures. In each unit pixel, a resistance value of the drain region of the transistor to drive a light-emitting device having the highest luminous efficiency among the transistors is higher than that of the drain region of a transistor to drive the light-emitting device having a relatively low luminous efficiency.

The invention discloses an organic light emitting display device, an organic light emitting display, and a method for reducing leakage current. The display comprises a plurality of display devices. The device comprises a plurality of sub pixel circuit units of which each is connected with a first TFT, the gates of the first TFTs are connected with a GATE line, and a first electrode of each first TFT is connected with the corresponding sub pixel circuit unit. Each organic light emitting display device comprises a second TFT of which the gate is connected with a GATE line, a first electrode is connected with a second electrode of each first TFT, and a second electrode is connected with a voltage V0. By configuring the TFTs between the pixel circuit and the voltage V0, the leakage current of the pixel circuit is reduced. Apart from the first TFTs, the TFTs of other levels are shared by all sub pixels belonging to the same pixel, which greatly reduces the number of TFTs, reduces the pixel area occupied by TFTs, can promote the PPI to meet the demands of PPT products, realizes display with higher-resolution, and enhances the quality of the display.

A display device includes an image display panel and a control device. The image display panel includes first sub-pixels, second sub-pixels, third sub-pixels, and fourth sub-pixels in which a specified sub-pixel column including the third sub-pixels and the fourth sub-pixels and at least one other sub-pixel column arranged next to the specified sub-pixel column are periodically arranged. The control device performs column inversion driving to apply a voltage having the same polarity to signal lines of a first specified sub-pixel column belonging to the specified sub-pixel columns and the other sub-pixel column adjacent to the first specified sub-pixel column, apply a voltage having the same polarity as the first specified sub-pixel column to one of the signal lines of a second specified sub-pixel column and a third specified sub-pixel column adjacent to the first specified sub-pixel column, and invert the polarities of the voltages to be applied at predetermined cycles.

The present invention provides a thin-film transistor and a fabrication method thereof, and an array substrate. The thin-film transistor includes a separation layer (5) arranged between the source electrode (4) and the drain electrode (6). An oxide semiconductor channel layer (7) is arranged on one side of the separation layer (5) and the drain electrode (6) to contact a portion of an upper surface of the drain electrode (6), a side surface of the drain electrode (6) and the organic separation layer (5), and a portion of an upper surface of the source electrode (4) to serve as a vertical channel, of which a channel length corresponds to a thickness of the separation layer (5). Varying the thickness of the separation layer to reduce the length of the vertical channel to a sub-micrometer order would greatly reduce the size of the thin-film transistor and reduce the area of a pixel. The vertical channel does not cause a short channel effect so as to improve electrical performance of the thin-film transistor. Using a multiple-layered hexagonal boron nitride film to make a moisture/oxygen barrier layer (2) and using a double-layered graphene film to make the source electrode (4) and the drain electrode (6) help significantly improve bending durability of the thin-film transistor.

The invention provides a TFT array substrate, a display device and a preparation method of the TFT array substrate. The TFT array substrate is provided with a double-layer storage capacitor structure,thus reducing the pixel area, improving PPI of a display panel, and increasing flexibility of layout design while ensuring the capacity of the storage capacitor of the TFT device and ensuring reliability of the TFT device. Besides, by setting an auxiliary metal layer between a first metal layer and a third metal layer, the insulating layers above and below the auxiliary metal layer can be simultaneously patterned through one patterning process, thus saving one mask, reducing the process of photo, etching and stripping of the patterning process, and saving the process cost of the TFT array substrate. The display device utilizes the TFT array substrate, so that under the same display size, the pixel distribution density of the display device is greatly improved and the displayed frame is clearer.

A 3TrCMOS solid-state image pickup device is provided with a plurality of pixels, including a first pixel (230) and a second pixel (231) adjacent to each other. Each of the adjacent pixels is provided with a photodiode (201) for converting light into a signal charge and a transmission transistor for reading out the signal charge generated by the photodiode (201). The first pixel (230) is provided with a reset transistor whose one end is connected with the both photodiodes (201) in the first pixel (230) and in the second pixel (231) and the other end is supplied with a power supply voltage. The second pixel (231) is provided with a gate electrode (204) connected with the both transmission transistors in the fist pixel (230) and the second pixel (231), and an amplifying transistor whose drain is supplied with a power supply voltage.

The invention discloses a packaging structure and a packaging method for a focal plane detector chip integrated pixel-level lens. The packaging structure comprises a packaging cover cap and a packaging base which are matched with each other, the packaging cover cap comprises a packaging cover cap body, a plurality of lenses and an inner concave cavity which are integrally formed, and the plurality of lenses are arranged in an array; the inner concave cavity is used for sealing and packaging a plurality of focal plane detector chips, the plurality of focal plane detector chips are all arranged on the packaging base, and meanwhile, the focus of a lens matched with one focal plane detector chip is distributed on a light receiving surface of the focal plane detector chip. The size of the packaging structure provided by the invention is greatly reduced; meanwhile, light within the range of the lens can be effectively converged and collected, signals are enhanced, noise is reduced, and the system performance is effectively improved.

A cost-effective image capture apparatus is presented which achieves high shutter speed without blurring the captured image or introducing noise. The apparatus uses standard 4T pixels to store exposure information on the pixel itself and employs a near simultaneous reset mechanism to reset the pixels, thereby achieving high-speed image capture without increasing the per pixel die area for extra storage or incurring unwanted current spikes and noise due to simultaneous resets.

The invention provides a display panel and a display device. The display panel comprises a normal display area and a special-shaped display area. A plurality of first pixel groups and first scanning lines are sequentially arranged in the normal display area; a plurality of second pixel groups and second scanning lines are sequentially arranged in the special-shaped display area; the second pixel group comprises a plurality of rows of sub-pixels arranged in the first direction, each row of sub-pixels are connected with the second scanning lines in the corresponding row, and each row of first scanning lines are connected with the second scanning lines in the corresponding row, so that the size of the sub-pixels in the second pixel group is reduced, the pixel density is improved, and the display quality is improved.

The invention provides a pixel circuit and an infrared imager, and relates to the field of infrared imaging. The integration module performs integration and coarse quantization through the common module and the charge injection module at the same time; the charge injection module injects charges into an integrating capacitor in the integrating module; the dynamic comparator generates a counting signal in the process of carrying out fine quantization on the residual voltage, the linear feedback shift register counter counts, the counting result is a coarse quantization result, the dynamic comparator generates the counting signal in the process of carrying out fine quantization on the residual voltage, the linear feedback shift register counter receives the counting signal and counts from 0, and the counting result is a fine quantization result. According to the pixel circuit, coarse and fine quantization share the same module, so that the pixel area is reduced. According to the pixel circuit, part of charges are injected into the integrating capacitor in stages, compared with the injection of equal charges, the introduced noise is lower, the noise charges injected every time are reduced on the whole, the signal-to-noise ratio is improved, and therefore the overall power consumption of the pixel circuit is reduced. The pixel circuit has lower power consumption and better quality factor.

The present disclosure relates to a thin film transistor substrate having a color filter layer. The present disclosure provides a thin film transistor substrate comprising: a plurality of pixel areas disposed in a matrix manner on a substrate, each pixel area including an aperture area and a non-aperture area; a first color filter and a second color filter stacked at the non-aperture area on the substrate; an overcoat layer disposed on the first color filter and the second color filter; a semiconductor layer disposed at the non-aperture area on the overcoat layer; a gate insulating layer and a gate electrode stacked on a middle portion of the semiconductor layer; a third color filter at the non-aperture area on the semiconductor layer and the gate electrode; and a source electrode and a drain electrode disposed on the third color filter.

The invention discloses an IGZO backboard structure applied to an OLED panel and a manufacturing method. A metal layer M0 is arranged on a substrate Sub; an insulating layer PV is also arranged on the substrate Sub, and the insulating layer PV covers the metal layer M0; a semiconductor layer IGZO is arranged on the insulating layer PV; a metal layer M0.5 is arranged on the IGZO semiconductor layer; an insulating layer GI is also arranged on the insulating layer PV and covers the metal layer M0.5 and the semiconductor layer IGZO; a metal layer M1 is arranged on the insulating layer GI; an insulating layer IP is also arranged on the insulating layer GI and covers the metal layer M1; a metal layer M2 is arranged on the insulating layer IP, and the metal layer M2 and the metal layer M0.5 form a storage capacitor; an organic flat layer OP is further arranged on the insulating layer IP, and the metal layer M2 is covered with the organic flat layer OP; an anode metal layer Anode is arranged on the organic flat layer OP; a pixel definition layer PDL is further arranged on the organic leveling layer OP, and an opening is formed in the position, at the anode metal layer Anode, of the pixel definition layer PDL. According to the invention, the defect of low resolution of the IGZO OLED panel can be improved.

A TOF image sensor pixel structure capable of suppressing background light is composed of a photodiode PD, a transmission switch TG, a feedback switch FBG, a reset switch rst, an MOS transistor capacitor C, a voltage-controlled current source and a charge integral amplification circuit. The negative electrode of the PD is connected with the charge integral amplification circuit through a transmission switch TG, and is connected with the MOS capacitor C and the control voltage Vctr of the voltage-controlled current source through a feedback switch FBG; the output current Ibias of the voltage-controlled current source directly flows into the negative electrode of the PD; the grid electrode of the MOS tube capacitor C is connected with the ground through a reset switch rst, and the source electrode and the drain electrode are in short circuit and are directly connected to the ground; and the structure can solve the problems that strong background light enables TOF pixels to be saturated and measurement precision to be reduced, and a traditional background light suppression scheme enables the pixel size to be significantly increased and enables the resolution of the sensor to be limited.

The invention provides a back plate. The back plate comprises a substrate, grid lines, data lines, power lines and pixel structures, wherein the grid lines, the data lines and the power lines are staggered in rows and columns, and the pixel structures are distributed in an array mode. The pixel structure comprises a driving transistor, a switching transistor connected with the driving transistor and a pixel electrode connected with the driving transistor, the grid line and the data line are respectively connected with the switching transistor, and the power line is connected with the driving transistor; in the same row of pixel structures or the same column of pixel structures, a power line is arranged between the (2n-1) th pixel structure and the (2n) th pixel structure, the power line is connected with a source electrode of the driving transistor in the (2n-1) th pixel structure, and the power line is connected with a source electrode of the driving transistor in the (2n) th pixel structure; n is a positive integer greater than or equal to 1. According to the invention, the pixel area can be saved, so that the driving transistors in the pixel structure can be reasonably arranged through the saved pixel area.