SOI MOS structure capable of resisting edge electric leakage and forming method thereof

Abstract

The invention discloses an SOI MOS structure capable of resisting edge electric leakage and a forming method thereof. The structure is characterized in that a heavily-doped region is arranged in a body contact region, the doping concentration of the heavily-doped region exceeds the doping concentration of a well region, the heavily-doped region comprises a partial boundary region between a body contact active region and a field injection region, and the edge of the heavily doped region is spaced apart from the gate region by a preset distance, so that the doping concentration of an included angle region between the body contact active region local edge field oxygen and the buried oxide layer exceeds the doping concentration of the well region, the injection window exposes the partial boundary region between the body contact active region and the field injection region, and a certain spacing distance is formed between the edge of the injection window and the gate region. Through the method, the parasitic transistor effect can be effectively inhibited, and a BTS-type SOI MOS structure capable of resisting edge electric leakage is formed.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an anti-edge leakage SOI MOS structure and a forming method thereof. Background technique [0002] SOI (Silicon On Insulator, silicon on insulator) is a silicon material with a special structure. SOI technology includes very rich content, such as materials, devices and integrated circuit manufacturing technologies. For SOI CMOS technology, due to the use of full dielectric isolation between devices, compared with bulk silicon technology, it has the advantages of no parasitic latch, high speed, low power consumption, high temperature resistance and radiation resistance. [0003] However, the leakage current of SOI MOSFET devices has always been an urgent problem to be solved in the industry. Currently commonly used isolation process technologies include junction isolation, LOCOS (Local Oxidation of Silicon, local oxidation isolation of silicon) technology, and STI (Shallow...

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Problems solved by technology

Although LOCOS and STI technologies have good isolation effects, they also introduce parasitic transistor effects. If the process is not handled properly or in an ionizing radiation environment, the parasitic transistors will be turned on, which will seriously affect the electrical characteristics of MOS devices.

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