Focal plane digitization pixel gain fine tuning circuit

A technology for fine-tuning circuits and focal planes, applied in televisions, electrical components, color TVs, etc., can solve the problems of large adjustment ratio deviation, large capacitance adjustment steps, and inability to fine-tune small capacitors to achieve accurate adjustment ratios and good adjustments Linearity, non-uniformity improvement effect

Active Publication Date: 2021-03-09
NO 24 RES INST OF CETC
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  • Abstract
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  • Application Information

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Problems solved by technology

[0003] The traditional method of numerical control to adjust the gain is to control the number of capacitors connected in parallel in the circuit through the switch of the MOS tube. Since the parasitic capacitance of the MOS tube itself is also at the fF level, it is in parallel with the adjusted capacitor, so this method In the adjustment of the tiny integral capacitance of the pixel in the readout circuit, the adjustment step of the capacitance will be too large, and the adjustment ratio will deviate greatly, making it impossible to fine-tune the small capacitance.

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  • Focal plane digitization pixel gain fine tuning circuit

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Embodiment Construction

[0018] The present invention will be further described below in conjunction with accompanying drawing.

[0019] In the description of the present invention, unless otherwise specified and limited, it should be noted that the term "connection" should be understood in a broad sense, for example, it can be a mechanical connection or an electrical connection, or it can be the internal communication of two elements, it can be Directly connected or indirectly connected through an intermediary, those skilled in the art can understand the specific meanings of the above terms according to specific situations.

[0020] like figure 1 As shown, it is a circuit diagram of a preferred embodiment of a focal plane digitized pixel gain fine-tuning circuit of the present invention, including a photodetector 1, a capacitance adjustment circuit 2, a comparator 3, a counter 4, a memory 5 and a data interface circuit 6 , the photodetector 1 is used to detect light signals and convert the light sig...

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Abstract

The invention discloses a focal plane digitization pixel gain fine tuning circuit, which comprises a photoelectric detector, a capacitance adjusting circuit, a comparator, a counter and a memory. Thephotoelectric detector is used for detecting an optical signal and outputting a current signal, and the capacitance adjusting circuit is used for adjusting the magnitude of an integrating capacitor connected to the fine tuning circuit. The comparator is used for receiving a current signal transmitted by the photoelectric detector and outputting an oscillation signal according to the current signal, the counter is used for counting the oscillation signal and storing the oscillation signal in the memory, and fine adjustment of the size of the integrating capacitor is realized through the capacitance adjusting circuit. Therefore, gain adjustment of pixels of the reading circuit during digital-to-analog conversion is realized, and imaging non-uniformity is improved.

Description

technical field [0001] The invention relates to the technical field of pixel gain adjustment, in particular to a focal plane digitized pixel gain fine-tuning circuit. Background technique [0002] The pixel gain non-uniformity in the focal plane readout circuit is an important source of image non-uniformity. The gain of the pixel is mainly determined by the size of the pixel integral capacitance. For the pulse frequency modulation (PFM) type digital readout circuit (DROIC), the integral capacitance of the pixel is extremely small, often only in the order of fF (10 -15 F), the integral capacitance is generally realized by wiring parasitic capacitance and MOS transistor gate parasitic capacitance. [0003] The traditional method of numerical control to adjust the gain is to control the number of capacitors connected in parallel in the circuit through the switch of the MOS tube. Since the parasitic capacitance of the MOS tube itself is also at the fF level, it is in parallel w...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N5/374H04N5/3745H04N5/378
CPCH04N25/77H04N25/76H04N25/75
Inventor 黄文刚曾岩
Owner NO 24 RES INST OF CETC
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