Multi-chip packaging structure and method for passive device stacking

Abstract

The invention provides a multi-chip packaging structure and method for passive device stacking. The structure comprises a metal layer, a bonding material, bare chips, conductive metal blocks, metal via holes, a rewiring layer, outer pins, passive devices, a conductive bonding material and an epoxy molding compound; the metal layer is used for connecting the passive devices; the bare chip is bondedwith the metal layer through the bonding material; the conductive metal block is arranged on the surface of the active region of the bare chip; the rewiring layers are connected with the conductive metal blocks; the rewiring layers are connected with adjacent rewiring layers, metal layer or packaging outer pin through the metal via holes or the conductive metal blocks; the passive devices are encapsulated in the epoxy molding compound; and the conductive bonding material is used for realizing electrical signal connection between the passive devices and the rewiring layer or the metal layer. According to the invention, the rewiring layer and the metal via holes are manufactured layer by layer, three-dimensional wiring is carried out in the epoxy molding compound, and a plurality of bare chips are embedded, so that the design of higher integration level and smaller boundary dimension in a single package is realized.

Description

technical field [0001] The invention relates to the technical field of chip design, in particular to a multi-chip packaging structure and method for stacking passive devices. Background technique [0002] As the critical dimensions of semiconductor integrated circuits continue to shrink, getting closer and closer to the technical limit of silicon materials, whether Moore's Law can continue has been greatly challenged. Heterogeneous integration through packaging technology is one of the ways to continue Moore's Law. At the same time, the miniaturization of electronic products and the increasingly tight product development cycle have put forward demands for the miniaturization and ease of use of integrated circuits. [0003] For example, in the traditional power management circuit, in addition to the DC-to-DC buck-boost chip (DC-DC) and the low-dropout linear regulator (LDO), peripheral devices are also required, such as: input and output capacitors, inductors, voltage regula...

AI Technical Summary

Problems solved by technology

[0004] At present, there are some passive device integration technologies in the industry, such as embedding passive devices into prefabricated organic substrates, but due to the limitation of substrate processing technology, the range of electrical parameters of components is limited

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