Memory system, memory controller and memory chip

Abstract

The invention discloses a memory chip, a memory controller and a memory system. The memory chip includes a memory block, an input / output data bus, and a plurality of first sense amplifiers. The plurality of first sense amplifiers are used for outputting a plurality of first data in parallel. A width of the input / output data bus is equal to a width of the plurality of first data output in parallel by the plurality of first sense amplifiers. Therefore, compared with the prior art, the power consumption, the access delay and the area of the memory chip can be reduced, and the reading / writing window tolerance of the memory chip can be improved.

Description

technical field [0001] The invention relates to a storage system, a storage controller and a storage chip, in particular to a storage system and a storage chip capable of parallel transmission of data between a logic circuit and the storage chip. Background technique [0002] Today, memory systems used in high-performance computing or artificial intelligence systems typically include dynamic random access memory chips and logic circuits. Due to the stack structure of the DRAM chip, the size of the DRAM chip cannot keep up with the size of the logic circuit. Therefore, a memory-wall effect occurs, resulting in a decrease in the data transfer rate between the logic circuit and the DRAM chip. In order to overcome the storage wall effect, the prior art usually uses a faster data rate (for example, from double data rate three (DDR3) to double data rate fourth (DDR4) or double data rate fifth (DDR5)) in the transfer data between the dynamic random access memory chip and the logi...

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Problems solved by technology

[0006] Although the prior art can reduce 4 clock delays (for example, to 3.5 clock delays) by optimizing the storage system 10, the serial serial-to-parallel conversion procedure performed by the above-mentioned serial-parallel circuit 23 and the above-mentioned parallel-serial circuit 314 perform The serial-to-serial conversion process requires extra power, transmission delay and die areas, resulting in low efficiency of the memory system 10

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