Wafer alignment method in photoetching process

Abstract

The invention discloses a wafer alignment method in a photoetching process, a wafer is provided with an alignment mark, the alignment mark is provided with a grating pattern, and the wafer alignment method comprises the following steps: 1, scanning a whole segment of alignment mark by adopting an alignment light source, and collecting a diffraction light signal corresponding to the whole segment of alignment mark to form a whole segment of alignment signal; 2, carrying out segmentation processing on the whole segment of alignment signal and forming each segment of alignment signal; 3, respectively calculating the MCC value and the WQ value of each segment of alignment signal; and 4, calculating an alignment point by adopting the segmented alignment signal with the best MCC value and WQ value so as to realize wafer alignment. The wafer rejection failure rate can be reduced, and the wafer rotation ratio can be improved.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing process method, in particular to a wafer (wafer) alignment method in a photolithography process. Background technique [0002] Integrated circuit manufacturing mainly includes lithography, etching, deposition, thin film, chemical mechanical polishing (CMP). Lithography is one of the most important pattern forming departments. [0003] The pattern formation of photolithography is mainly glue coating, exposure and development. Every step is important and cannot be separated. [0004] The process tools of lithography are mainly track and exposure tool. [0005] In the photolithography process, the wafer will first be glued in the track machine, and then exposed in the exposure machine, and then developed in the track machine after exposure, and the photoresist pattern will be formed after development. [0006] The exposure machine mainly uses the laser to pass through the mask t...

AI Technical Summary

Problems solved by technology

[0018] Wafer reject fail often occurs in existing methods due to lithographic alignment, especially in power (Power) device products in the top metal layer (Top metal), passivation layer (Passivation) and polyamide The reject fail ratio of the polyimide layer is very high during photolithography exposure, which requires rework, resulting in a decrease in the wafer turn ratio, increasing the cost of the wafer, and even causing the risk of scrapping the wafer due to misjudgment

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