[0052]Such asimage 3 As shown, it is a flow chart of the wafer alignment method in the light engraving process of the embodiment of the present invention;Figure 5As shown, it is a segment parallel signal curve in the embodiment of the present invention; in the photolithographic method of the photolithography process, the wafer has a pair mark on the wafer, the pair mark. The wafer counterpart method includes the following steps:
[0053]Step 1, the opposite source scanning segment is used, and the display of the derived light signal corresponding to the entire segment to form a whole pair signal 1 is formed.Figure 5Only part of the entire alignment signal 1 is only shown.
[0054]Step 2, the entire segment block signal 1 is segmented and form each segmentatic opposite signal.Figure 5Only three segmented parallel signals are shown, and it is derived from markers 1a, 1b, and 1c, respectively.
[0055]Step three, calculate the MCC value and the WQ value of each of the segmented opposite signals.
[0056]This is not calculated to calculate the MCC value and the WQ value of the entire alignment signal 1. If the MCC value and the WQ value of the entire alignment signal 1 are calculated, it is possible to reject the exposure machine directly.
[0057]Step 4, using the MCC value and the best segmented parallel signal of the WQ value to calculate the alignment to achieve the wafer opposition.
[0058]In the embodiment of the present invention, the segmented pairs of position signals 1a, 1b, and 1c calculate the corresponding MCC value and the WQ value, respectively, only 3 of the MCC values and WQ values corresponding to the three segments can achieve crystal. Circular opposition. Selecting the MCC value and the best SP value of the WQ value to calculate the alignment to minimize the removal of the wafer refusal failure.
[0059]In the embodiment of the present invention, prior to step one, it is also included whether there is damage to whether or not the topography of the opponent marker is damaged. If there is a damage, the starting step is used to perform the wafer alignment by one to step four described above. When the step is judged, it is judged that the object of the opponent tag is intact, then the alignment signal using the entire pair bit signal 1 or the opposite mark center in the step one is used. The judgment step can be used to perform wafer pairs in the case where the surface topography is intact, which can improve the wafer pair efficiency.
[0060]If in the step 4, the wafer is successfully opposed, and the wafer is exposed. Preferred, the steps of the wafer alignment method are disposed in the first exposure process menu, and the first exposure process is directly called directly before the step of determining the topography of the opposite mark. The menu is handled.
[0061]If the wafer opposing fails, the exposure of the wafer is rejected.
[0062]In the embodiment of the present invention, the steps are followed by the steps:
[0063]Opponten to the observing;
[0064]The coarse alignment of the wafer is carried out.
[0065]The wafer opposition method is completed in the exposure machine, and the wafer is fixed on the chuck.
[0066]In the embodiment of the present invention, the pair is labeled as a front layer pair mark corresponding to the photolithography of the wafer.
[0067]The semiconductor device formed on the wafer includes a power device.
[0068]The photoresist layer includes a top metal layer, a passivation layer, and a polyimide layer.
[0069]The segmentation structure in which the highlier densive light enhancement is also provided in the grating period of the opposite position. The level of the enhanced diffraction light of the opposite position is included in Level 3, Level 5 or 7. Now combinedFigure 4 The pair of pairs of pairs are further illustrative:
[0070]Such asFigure 4 As shown, it is a pair marker layout of the model of CT-AH53 in the embodiment of the present invention; the opposition mark 301 is a strip structure having a length of 747 μm and a width of 80 μm.
[0071]There is a grating pattern in the counterpart mark 301, a bar pattern 304 in the grating period; strip pattern 304 refers to the enlarged pattern 303 of the right side portion of the bit mark 301, and the enlarged pattern 303 also marks the corresponding size.
[0072]As can be seen from the amplification pattern 302 of the central region of the counterpart mark 301, there is also a fine structure in the strip pattern 304, specifically with three strips 305 and 2 spacing, which can achieve the 5th level diffracted light. Light intensity
[0073]The grating period of the counter-position labeled grating is 16 μm or 17.6 μm.
[0074]The counterpart label is disposed on the scribe groove of the wafer.
[0075]Since the existing method is to perform the alignment of the alignment signal of the entire alignment signal or the center of the center of the bit mark, the distortion generated by damage is presented in the counter mark. The signal 1 is not up to the standard and the rejection of subsequent exposure is rejected, and the alignment signal of the center of the bit mark is also easy to generate; and the embodiment of the present invention performs segmentation and forming each of the segmented signal 1. The segmentally opposition signal, then calculate the MCC value and the WQ value of each segment signal, and select the MCC value and the best segmented segmentation signal of the WQ value to calculate the peer point to achieve the wafer opposition, so that even There is damage in the bit mark, but as long as there is a complete damaged segment in the entire pair mark, the grating pattern in the segment is sufficient to achieve a good positioning, and finally reduce the wafer refusal to receive the failure rate, improve the crystal Circular rotation ratio.
[0076]The present invention will be described in detail by the specific embodiments, but these are not constituting the limitation of the invention. Many modifications and improvements in the art can also be considered as the scope of the invention without departing from the principles of the invention.
