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Enhanced power semiconductor device structure and preparation method thereof

A technology of power semiconductor and device structure, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as unstable performance and complex structure

Pending Publication Date: 2021-04-16
GUANGDONG INST OF SEMICON IND TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In order to solve the problem of unstable performance and complex structure of enhanced power semiconductor devices when their breakdown voltage is increased, the inventors, after a lot of research and experiments, found that the p-GaN gate of the enhanced power semiconductor device using p-GaN gate Designed as a stepped structure, which can make the electric field distribution between the p-GaN gate and the drain electrode more gentle, thereby improving the breakdown voltage of the enhanced power semiconductor device

Method used

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  • Enhanced power semiconductor device structure and preparation method thereof
  • Enhanced power semiconductor device structure and preparation method thereof
  • Enhanced power semiconductor device structure and preparation method thereof

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preparation example Construction

[0072] refer to Figure 9 As shown, the preparation method is applied to prepare the enhanced power semiconductor device structure mentioned in any of the foregoing embodiments, including steps:

[0073] Step S1: preparing a first substrate;

[0074] Step S2: growing a high-resistance layer and a barrier layer sequentially on the first substrate, and forming a heterojunction with 2EDG between the high-resistance layer and the barrier layer;

[0075] Step S3: growing a p-type gate layer on the barrier layer;

[0076] Step S4: Etching the p-type gate layer to form a p-type gate with a stepped structure, wherein the stepped structure formed by etching includes a step with a maximum thickness and a step toward the step with a maximum thickness at least one thinned mesa stage extending on at least one side, with a maximum thickness configured to deplete the 2DEG in the underlying heterojunction;

[0077] Step S5: Prepare the drain electrode on the side of the thinned mesa stage ...

Embodiment 1

[0099] References to the steps of the processing method in this embodiment Figure 12 as shown,

[0100] The first step is to select a substrate made of sapphire;

[0101] The second step is to use MOCVD technology to deposit a buffer layer of AlN / GaN on the surface of the sapphire substrate;

[0102] In the third step, a high-resistance layer made of GaN and a barrier layer made of AlGaN are sequentially deposited on the surface of the buffer layer by MOCVD technology to form a 2DEG layer between the high-resistance layer and the barrier layer on the surface of the buffer layer. Heterojunction;

[0103] The fourth step is to use MOCVD technology to deposit a p-type gate layer made of GaN on the surface of the barrier layer;

[0104] The fifth step is to perform a first etching on the p-type gate layer by ICP technology to form the first gate layer structure;

[0105] The sixth step is to perform a second etching on the first gate structure by using ICP technology to form ...

Embodiment 2

[0109] The difference between this embodiment and Embodiment 1 is mainly in the fourth step and the sixth step, which are specifically realized as follows:

[0110] In the fourth step, an N-polar p-type gate layer made of GaN is deposited on the surface of the barrier layer by MOCVD technology;

[0111] In the sixth step, a second etching is performed on the first gate structure by using a wet etching process to form a p-type gate with a stepped structure.

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Abstract

The invention discloses an enhanced power semiconductor device structure and a preparation method thereof, and the device comprises a heterojunction with 2 DEG; a source electrode which is located above the heterojunction, a p-type gate and a drain electrode are of a stepped structure. and a gate electrode which is arranged on the p-type gate. At least part of the step sections in the stepped structure are thinning step sections extending towards the drain electrode side with the step section with the largest thickness of the p-type gate as the starting point, the gate electrode is arranged on the step section with the largest thickness of the p-type gate, and the thickness of the step section with the largest thickness is set to enable 2DEG in the heterojunction located below the gate electrode to be exhausted. According to the technical scheme, the 2DEG density difference in the heterojunction below the adjacent step sections, especially the 2DEG density difference between the heterojunction on the p-type gate drain electrode side and the heterojunction below the adjacent step sections, is reduced, and the problem that the breakdown voltage is reduced due to the fact that a 2DEG density abrupt change interface exists in an electric field between a gate and a drain is solved.

Description

technical field [0001] The invention relates to the technical field of enhanced power semiconductor devices, in particular to an enhanced power semiconductor device structure and a preparation method thereof. Background technique [0002] Compared with traditional Si-based power semiconductor devices, the third-generation semiconductor materials have higher power density when used in power semiconductor devices due to their wider forbidden band width. When these third-generation semiconductor materials with wide band gaps are used in high electron mobility transistors (High Electron Mobility Transistor, referred to as HEMT), the inherent polarization characteristics (spontaneous polarization and Piezoelectric polarization) to generate two-dimensional electron gas (2DEG) with high concentration and high electron mobility, which makes HEMT have higher switching frequency and smaller on-state resistance, thus making it possible to manufacture A HEMT with a smaller size can be ...

Claims

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Application Information

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IPC IPC(8): H01L29/778H01L21/335H01L29/423H01L29/06
CPCY02B70/10
Inventor 曾巧玉李成果姜南尹雪兵葛晓明曾昭烩陈志涛
Owner GUANGDONG INST OF SEMICON IND TECH
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