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Semiconductor device and forming method thereof, vertical double diffused metal oxide semiconductor (VDMOS) transistor and forming method of VDMOS transistor

A semiconductor and device technology, applied in the field of semiconductor manufacturing, can solve the problem of breakdown voltage occurring in the p-well region of the sub-edge, and achieve the effect of preventing breakdown

Active Publication Date: 2015-04-01
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] The problem solved by the present invention is to provide a semiconductor device and its forming method, a VDMOS transistor and its forming method, so as to solve the problem that the breakdown voltage of the semiconductor device easily occurs on the p-well region of the secondary edge in the existing technology, and improve the reliability of the entire semiconductor device. Pressure capacity

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  • Semiconductor device and forming method thereof, vertical double diffused metal oxide semiconductor (VDMOS) transistor and forming method of VDMOS transistor
  • Semiconductor device and forming method thereof, vertical double diffused metal oxide semiconductor (VDMOS) transistor and forming method of VDMOS transistor
  • Semiconductor device and forming method thereof, vertical double diffused metal oxide semiconductor (VDMOS) transistor and forming method of VDMOS transistor

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Embodiment 1

[0045] Figure 6 to Figure 11 It is a schematic diagram of the first embodiment of forming a semiconductor device according to the present invention.

[0046] Such as Figure 6 As shown, a semiconductor substrate 410 is provided; an epitaxial layer 412 is formed on the surface of the semiconductor substrate 410 .

[0047] In this embodiment, the conductivity type of the epitaxial layer 412 is the same as that of the semiconductor substrate 410 . For example, the semiconductor substrate 410 is n + type substrate, the epitaxial layer 412 is n - Punishment epitaxy layer. The doping concentration of the semiconductor substrate 410 is greater than the doping concentration of the epitaxial layer 412 . The methods for forming the epitaxial layer 412 include molecular beam epitaxy (MBE), ultra-high vacuum chemical vapor deposition (UHV / CVD), atmospheric pressure epitaxy (ATM Epi) and reduced pressure epitaxy (RP Epi).

[0048] Such as Figure 7 As shown, a silicon oxide layer 4...

Embodiment 2

[0076] Figure 16 to Figure 21 It is a schematic diagram of a second specific embodiment of forming a semiconductor device according to the present invention.

[0077] Such as Figure 16 As shown, a semiconductor substrate 510 is provided; an epitaxial layer 512 is formed on the surface of the semiconductor substrate 510 .

[0078] In this embodiment, the conductivity type of the epitaxial layer 512 is the same as that of the semiconductor substrate 510 . For example, the semiconductor substrate 510 is n + type substrate, the epitaxial layer 512 is n - Punishment epitaxy layer. The specific process of forming the epitaxial layer 512 is as described in the first embodiment.

[0079] Such as Figure 17 As shown, a silicon oxide layer 514 and a silicon nitride layer 515 are sequentially formed on the epitaxial layer 512 to form a core device region I and an edge region II.

[0080] In this embodiment, the specific process of forming the core device region I and the edge re...

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Abstract

The invention discloses a semiconductor device and a forming method thereof, a vertical double diffused metal oxide semiconductor (VDMOS) transistor and a forming method of the VDMOS transistor. The forming method of the semiconductor device comprises the following steps of: providing a semiconductor substrate, wherein the semiconductor substrate comprises a core device area and a marginal area, and an epitaxial layer is formed on the semiconductor substrate; forming a gate dielectric layer and a polysilicon layer on the epitaxial layer in sequence; etching the polysilicon layer and the gate dielectric layer until the epitaxial layer is exposed to form a polysilicon gate, wherein the width of the polysilicon gate adjacent to the marginal area is minimum; performing ion implantation on the semiconductor substrate by taking the polysilicon gate as a mask; and forming a well area in the epitaxial layer between the polysilicon gates, wherein a distance between the two adjacent well areas is a node distance, and the node distance closest to the marginal area is minimum. By the semiconductor device and the forming method thereof, the VDMOS transistor and the forming method of the VDMOS transistor, the breakdown voltage can be effectively prevented on the sub-marginal well area, so that the voltage endurance capability of the overall semiconductor device is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and its forming method, a VDMOS transistor and its forming method. Background technique [0002] With the continuous development of semiconductor process technology, products based on BCD (Bipolar / CMOS / DMOS) can integrate complex control functions, making it a mainstream process technology for power integrated circuits. The BCD process can select different devices for different circuits to optimize the corresponding sub-circuits, and realize the requirements of low power consumption, high integration, high speed, high driving capability, and high current of the entire circuit. [0003] High-voltage MOS transistors appearing in the existing BCD process include LDMOS (Lateral Double-diffused Metal-Oxide-Semiconductor) transistors and VDMOS (Vertical Double-Diffused Metal-Oxide-Semiconductor) transistors. where in VDMOS transistors, such as figure ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8234H01L27/088H01L21/336H01L29/78H01L29/06
Inventor 苟鸿雁
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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