Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Method for shortening sensing delay, multiplexer and nonvolatile memory read circuit

A read circuit and non-volatile technology, applied in the field of delay period circuits, multiplexers and non-volatile memory read circuits, can solve the problem of increasing the inherent resistance of address lines and sense amplifiers, reducing address line and sense amplifier gain issues

Pending Publication Date: 2021-04-23
SEMICON COMPONENTS IND LLC
View PDF1 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When higher voltages are used to charge the address lines, the resulting high temperature inherently reduces the gain and increases the inherent resistance of the address lines and sense amplifiers

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for shortening sensing delay, multiplexer and nonvolatile memory read circuit
  • Method for shortening sensing delay, multiplexer and nonvolatile memory read circuit
  • Method for shortening sensing delay, multiplexer and nonvolatile memory read circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0033] Various embodiments described herein relate to circuits and methods configured to shorten a delay period associated with reading a selected NVM cell. Such as figure 1 As shown, a prior art non-volatile memory (NVM) read circuit 100 typically operates on an array 100 of memory cells (herein "bit cells") 102 . Bit cells 102 are typically arranged in rows and columns with "M" rows and "N" columns (where M and N are integers), for example, bit cells 102(1x1), 102(1x2) through 102(MxN) . Any number of rows and columns can be used for array 101, and other formats can also be used. Each bit cell can be selected individually by using address decoder 104 , row M driver 106 and column N driver 108 . Each bit cell is typically coupled via a pair of bit lines 110 (MxN) and 111 (MxN) to a multiplexer ("MUX") 112 providing a respective read switch S1 to S6. When the read switch is selected by MUX 112, the read switch is closed and the data stored on the selected bit cell ("bit ce...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a method for shortening a sensing delay, ,a multiplexer and a nonvolatile memory read circuit. Devices, systems, and methods for reducing sensing delays for a non-volatile memory reading circuit may include operations for pre-charging a plurality of bit lines coupling a memory array having multiple bit cells with a sensing amplifier. Upon receiving a read request identifying a given bit cell in the memory array, the addressed bit line is decoupled from a bias voltage. The addressed bit line corresponds to the given bit cell and is selected from the plurality of bit lines. With the decoupling from the bias voltage, the addressed bit lines are coupled to the sensing amplifier. After a sensing circuit delay, data stored in the given bit cell is provided to the sensing amplifier via the addressed bit lines coupled to the sensing amplifier. The data stored in the given bit cell may then be interpreted by the sensing amplifier and a corresponding data output signal is generated.

Description

[0001] Cross References to Related Applications [0002] This application claims U.S. Serial No. 62 / 924,696, entitled "High Temperature FreeProm Advanced Reading Circuitry," filed October 23, 2019, and titled "High Temperature FreeProm Advanced Reading Circuitry," by Ivan Koudar (I. Koudar) as the inventor Priority of the provisional application, which is hereby incorporated by reference in its entirety. This application also claims "Non-Volatile Memory Reading Circuits and Methods for Reducing Sensing DelayPeriods" filed on September 30, 2020 and entitled "Non-Volatile Memory Reading Circuits and Methods for Reducing Sensing DelayPeriods" by Ivan Koudar (I. Koudar) as the inventor. Non-Volatile Memory Read Circuits and Methods), which has applicant docket number ONS04138US, is incorporated herein by reference in its entirety. technical field [0003] The techniques described herein relate generally to methods of reducing sensing latency, multiplexers, and non-volatile memory...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G11C7/10G11C7/22G11C7/06G11C8/10G11C8/18
CPCG11C7/1051G11C7/22G11C7/062G11C8/10G11C8/18G11C16/26G11C16/24G11C7/12G11C7/1012G11C7/04G11C2207/002G11C7/08
Inventor I·考达尔
Owner SEMICON COMPONENTS IND LLC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com