Power chip stacking and packaging structure

Abstract

The invention discloses a power chip stacking and packaging structure. The power chip stacking and packaging structure comprises a metal sheet, a first chip, a lead wire frame and a second chip which are stacked in sequence to form a stacking structure, and a packaging body for packaging the stacking structure, wherein the lead wire frame comprises a base island, a first pin electrically connected with the base island, and a second pin insulated from the base island; two opposite sides of the first chip are provided with a first electrode and a second electrode, and two opposite sides of the second chip are provided with a third electrode and a fourth electrode; the metal sheet and the first electrode, the second electrode and the base island, and the base island and the third electrode are respectively combined through conductive combination layers; the fourth electrode is electrically connected with the second pin; and the front surface of the metal sheet, a part of the first pin and a part of the second pin are exposed out of the package body. According to the power chip stacking and packaging structure, the two chips are fixed on the two opposite sides of the lead wire frame for stacking and packaging, and the metal sheets are exposed, so that the size of the packaging structure is reduced, and meanwhile, the packaging structure has better heat dissipation performance.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a power chip stack package structure. Background technique [0002] At present, the development trend of semiconductor packaging is developing towards the direction of multi-chip packaging. Stacked package is a type of multi-chip package. Small package size and good heat dissipation performance are the development trend of power chip stack package structure. [0003] The existing power chip stack package structure, one is to package different chips in different packages, then stack the packages, and realize the interconnection between multiple chips through perforation, solder balls, etc. to form the final whole Packaging structure: In this power chip stacking packaging structure, each chip requires a substrate to carry, and each chip needs to be packaged. The size of the packaging structure is large, which is not conducive to the miniaturization design of the product. ...

AI Technical Summary

Problems solved by technology

[0003] The existing power chip stack package structure, one is to package different chips in different packages, then stack the packages, and realize the interconnection between multiple chips through perforation, solder balls, etc. to form the final whole Packaging structure: In this power chip stacking packaging structure, each chip needs a substrate to carry, and each chip needs to be packaged. The size of the packaging structure is large, which is not conducive to the miniaturization design of the product

[0004] Another power chip stack package structure, two or more chips are packaged in the same package, and the electrodes of the chips are electrically connected to the pins through copper wires to lead the chip electrodes to the outside; however, there are For the double-sided electrode chip of the electrode, when two or more double-sided electrode chips need to be stacked and packaged, it is difficult for this package structure to realize the interconnection between chips and the external lead of electrodes.

[0005] Moreover, the above two power chip stack package structures cannot achieve efficient heat dissipation

[0006] In the prior art, there is a lack of a power chip stack package structure that can stack chips with electrodes on both sides, and can solve the problem of large power chip stack package structure size and poor heat dissipation performance.

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