Bit synchronizing circuit having high synchronization characteristics

Abstract

A bit synchronizing circuit is arranged by a bit synchronization counter constructed of an up / down counter or an adding / subtracting counter; an edge detector for detecting an edge of an input NRZ signal to output an edge detection pulse; two sets of edge number counters for counting total numbers of edge detection pulses outputted from the edge detector during a 1 cycle of the counting operation by the bit synchronization counter; and two sets of registers for fetching the count value of the bit synchronization counter at the time instant every time the edge detector outputs the edge detection pulse, and also for storing an accumulation value of the count values fetched during the 1 cycle of the counting operation by the bit synchronization counter. Both the two edge number counters and the two registers are operated with shifts of a half cycle, respectively. This bit synchronization circuit is further arranged by a judging circuit for judging a synchronization shift amount between the input NRZ signal and the counting operation by the bit synchronization counter based on the count values of the two edge number counters and the accumulate values stored in the two registers, and for outputting a correction signal corresponding to the judgment result to the bit synchronization counter.

Description

technical field [0001] The present invention relates generally to bit synchronization circuits used in communication facilities, and more particularly to bit synchronization circuits of high synchronization characteristics employed, for example, in paging receivers. Background technique [0002] Various types of paging receivers have appeared on the market. For example, in a paging receiver capable of receiving POCSAG (Postal Code Standard Advisory Group) or paging signals, that is, FSK (frequency shift keying) modulated paging signals, the received FSK signals are changed to NRZ (non-return to zero) ) binary signal, and then convert it into digital data according to the identification of whether the NRZ binary signal is high or low. In order to correctly convert the FSK signal into digital data (ie, data demodulation), the level discrimination of the binary signal is preferably performed near the center point in each bit period (ie, the duration period of 1-bit data). To ...

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Problems solved by technology

In other words, there is such a disadvantage that a lengthy time is bound to be required up to a synchronous situation from an asynchronous situation, for example, as in a paging receiver just after the power is turned on.

[0006] Moreover, since the above-mentioned conventional bit synchronizing circuit is configured so that the two edge number counters 2 and 3 count every predetermined value, even if the count values ​​of the edge number counters 2 and 3 are set to a large value, , there is still an unavoidable interval where the up / down counter 4 needs to correct the count value according to the noise contained in the input signal

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