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Preparation method of full-self-aligned high-density 3D multilayer memory

A memory and self-alignment technology, used in semiconductor devices, electrical solid-state devices, electrical components, etc., can solve the problems of memory density limitation, the inability to guarantee the consistency of the thickness of the storage medium, etc., and achieve the effect of preventing short circuits and low storage density.

Active Publication Date: 2021-06-18
CHENGDU PPM TECH LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The minimum width of both will determine the minimum value of the memory cell area on the same layer, as a result, the memory density is limited by the process level
[0007] Chinese patent application CN101615656A discloses a non-volatile storage device and its manufacturing method, see its Figure 11 , the thickness of the storage medium (150) or buffer layer (162), as a key parameter affecting the performance of the device, depends on the control of deep groove etching technology, and cannot guarantee the storage medium (150) or buffer layer in each layer of memory cells The thickness of layer (162) is consistent, also there is aforementioned problem simultaneously

Method used

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  • Preparation method of full-self-aligned high-density 3D multilayer memory

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Embodiment Construction

[0048] The preparation method of the present invention comprises the following steps:

[0049] 1) Form the basic structure: see Figure 2 ~ Figure 4 , a predetermined number of conductive medium layers and insulating medium layers are arranged in such a manner that the conductive medium layers and the insulating medium layers overlap each other to form a basic structure. In the actual process, the basic structure is set on the substrate and the underlying circuit, such as Figure 4 shown. Figure 4 Among them, 42 is an insulating medium layer, 41 is a conductive medium layer, 43 is a bottom circuit, and 44 is a substrate.

[0050] 2) Slot the base structure: see Figure 5 , Figure 6 , on the basic structure body, a curved dividing groove is opened from the top layer to the bottom layer, and the dividing groove divides the basic structure body into two staggered and mutually separated interdigitated structures; Figure 6 for Figure 5 A--A' sectional schematic diagram. ...

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Abstract

The invention discloses a preparation method of a fully-self-aligned high-density 3D multilayer memory, and relates to a preparation technology of memories. The method comprises the following steps: 1) forming a basic structure body; 2) slotting the basic structure body; 3) filling an insulating medium in the obtained segmentation groove; 4) performing deep hole etching on the insulating medium filled in the step 3) to form storage unit holes which are discretely arranged along the segmentation groove, arranging the insulating medium between the adjacent storage unit holes, and exposing the basic structure body part in the storage unit holes; and 5) arranging each layer of medium required by the preset memory structure in the memory unit hole layer by layer. The semiconductor memory prepared by the technology of the invention has high storage density.

Description

technical field [0001] The invention relates to the preparation technology of memory. Background technique [0002] Existing technologies include Erasable Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), Flash Memory, NAND-Flash Memory, Hard Disk, Compact Disk (CD), Digital Versatile Disc (DVD) Various digital storage technologies, including the Blu-ray Disc registered by the Blu-ray Disc Association, have been widely used for data storage for more than 50 years. However, the lifetime of storage media is generally less than 5 to 10 years. The antifuse storage technology developed for big data storage cannot meet the needs of massive data storage because of its high cost and low storage density. [0003] Chinese patent application CN101447502A discloses a non-volatile storage device and its manufacturing and use methods, see its Figure 11 to Figure 14 , the key process steps are: setting the data storage layer 130 on the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/112
CPCH10B20/00Y02D10/00H10B99/16H10B63/845H10B20/40H01L21/311H01L29/66143
Inventor 彭泽忠王苛
Owner CHENGDU PPM TECH LTD