Reduced parasitic resistance and capacitance field effect transistor

Abstract

A field effect transistor and method for making the same is described wherein the field effect transistor incorporates a T-shaped gate and source and drain contacts self-aligned with preexisting shallow junction regions. The present invention provides a low resistance gate electrode and self-aligned low resistance source / drain contacts suitable for submicron FET devices, and scalable to smaller device dimensions.

Description

field of invention [0001] The present invention relates to semiconductors, and more particularly to self-aligned metal oxide semiconductor (MOS) field effect transistors (FETs) with T-shaped gates of submicron gate length. technical background [0002] Metal-oxide-semiconductor (MOS) field-effect transistor (FET) technology requires shrinking the gate length to less than 0.25 μm. The standard process for gate formation is to deposit a layer of polysilicon, etch this layer to define the desired gate length, and perform source / drain shallow implant steps using the polysilicon as a mask. The shallow implant step is followed by formation of nitride sidewall spacers, implantation of deep ohmic regions in the source / drain regions, and then formation of gate and source / drain implanted metal silicides. Thus as the gate length decreases, the resistance of the gate increases since the gate metal suicide has the same gate length as the underlying polysilicon gate. Gate resistance slo...

AI Technical Summary

Problems solved by technology

Higher resistance associated with thinner silicide source / drain contacts further degrades the speed performance of the FET

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