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CLOCK AND DATA RECOVERY CIRCUITRY, and operation method thereof

A clock data recovery and circuit technology, applied in the direction of electrical components, automatic power control, etc., can solve problems such as large power consumption, heavy system load, etc.

Pending Publication Date: 2021-07-13
光程研创股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, because the CDR operates at high frequency, the traditional frequency detector will consume a lot of power and bring a heavy load to the system

Method used

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  • CLOCK AND DATA RECOVERY CIRCUITRY, and operation method thereof
  • CLOCK AND DATA RECOVERY CIRCUITRY, and operation method thereof
  • CLOCK AND DATA RECOVERY CIRCUITRY, and operation method thereof

Examples

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Embodiment Construction

[0019] In data communication, such as serial communication of digital data, when data transmission does not provide a reference clock signal, clock data recovery is required. If the receiver does not have a reference clock signal, the receiver may over- or under-sample the data and thus bit errors may occur. While there are oversampling and / or undersampling issues, there is still a need for sending data without a reference clock signal. One reason for this is because there is limited space (eg, bandwidth) in the signal to carry data. Due to space constraints, in order to transmit more data at a faster rate, it is necessary to reduce unnecessary data transmitted on the signal. The unnecessary data may be overhead data, such as a reference clock signal. In other words, the transmitted signal should not be filled with overhead data, but should aim to carry as much necessary data as possible.

[0020] As a result, clock data recovery (CDR) techniques are gaining in importance a...

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PUM

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Abstract

The invention relates to a clock and data recovery circuitry, and an operation method thereof. Introduced here are techniques for implementing a clock and data recovery circuit with improved tendencies, such a pull up and / or pull down tendencies. In various embodiments, the CDR circuit includes a phase detector that receives an input signal and outputs a reference clock signal. The phase detector then outputs two signals to charge pump. The output from the charge pump drives an oscillator control voltage up or down depending the current from the charge pump. A lock detector detects whether a lock has occurred by comparing the oscillator control voltage to a predetermined threshold voltage. A lock can occur when the circuit has settled into a frequency substantially near the frequency of the input signal and the oscillator control voltage is substantially near the threshold voltage. A controller circuit can control a sweeping of an available frequency range by the circuit until a lock occurs.

Description

technical field [0001] The present invention relates to analog circuit design, in particular to a clock data recovery circuit. Background technique [0002] In order to increase the data transmission rate and reduce the overhead (overhead), communication systems are continuously improved. One of the common improvements is to transmit data without providing a reference clock. Therefore the receiver must process the data asynchronously, so that the clock and the data can be recovered without a reference clock. The receiver may utilize a Clock and Data Recovery (CDR) circuit to perform asynchronous data processing. Typically a CDR circuit uses a frequency detector to track the input data rate and to match the frequency of the VCO to the input data rate. Also, the CDR can use a phase detector to detect the phase difference between the input data rate and the generated clock, and lock the phase accordingly. In this way, CDR can match the frequency of the output signal to the ...

Claims

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Application Information

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IPC IPC(8): H03L7/08
CPCH03L7/08
Inventor 林绍弘
Owner 光程研创股份有限公司