SGT device with silicon nitride barrier layer and method of making

Abstract

The invention provides a SGT device with a silicon nitride barrier layer and a preparation method thereof, comprising a metallized drain, an N+ substrate, an N-drift region, and a metallized source that are sequentially stacked from bottom to top; in the N-drift region It has a trench gate structure, a P-type doped region, a P+ heavily doped region, and an N+ heavily doped region; the trench gate structure includes an oxide layer, a control gate electrode, a silicon nitride barrier layer and a shield gate electrode; when the device is forward When on, the control gate electrode is connected to positive potential, the metallized drain is connected to positive potential, and the metallized source is connected to zero potential; when the device is reversely blocked, the control gate electrode and metallized source are shorted and connected to zero potential, and the metallization The drain is connected to a positive potential; the invention has characteristics such as larger forward current, smaller threshold voltage, and smaller on-resistance, and effectively solves the reliability problem of unstable breakdown voltage of SGT.

Description

technical field [0001] The invention belongs to the technical field of power semiconductors, and in particular relates to an SGT device with a silicon nitride barrier layer and a preparation method thereof. Background technique [0002] Since Dr. Zeng Jun of Fairchild Semiconductor proposed Shield-gate VDMOS in 2003, this device with low specific on-resistance and low gate charge has attracted widespread attention. The device introduces a new electrode in the conventional groove gate VDMOS groove, which can be used as a field plate-assisted depletion device in the drift region of the carrier to reduce the specific on-resistance of the device, and can also act as a shield to reduce the interaction between the gate electrode and the drain electrode. The stack area reduces the Miller capacitance of the device and reduces the gate charge. Compared with traditional VDMOS devices, shielded gate VDMOS devices have the advantages of low power loss, small parasitic capacitance, fast...

AI Technical Summary

Problems solved by technology

This causes the avalanche breakdown voltage of the SGT device to increase first and then decrease with the increase of the stress time. As the stress time increases, when the avalanche breakdown voltage of the device is lower than the system operating voltage, the device is prone to failure and affects the entire system. run

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