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Joint simulation optimization method for on-chip power supply distribution network

A technology of power distribution and co-simulation, applied in the direction of design optimization/simulation, special data processing applications, etc., can solve the problems of discontinuous circuit design and optimization, time-consuming and time-consuming for researchers, and simplify the manual design process , The effect of promoting the process of industrialization

Pending Publication Date: 2021-08-13
HANGZHOU DIANZI UNIV
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AI Technical Summary

Problems solved by technology

[0005] However, due to the discontinuity and non-differentiability of circuit design and optimization, the high complexity of contemporary large-scale circuit design and optimization will cost researchers a lot of time and energy. Therefore, it is necessary to provide a more efficient parameter design and structural optimization. method to solve the current problem of heavy and time-consuming electromagnetic design optimization process. On the other hand, this method will be of great significance to promote the wider application of EBG structures in electromagnetic problems.

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  • Joint simulation optimization method for on-chip power supply distribution network
  • Joint simulation optimization method for on-chip power supply distribution network
  • Joint simulation optimization method for on-chip power supply distribution network

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Embodiment Construction

[0032] The present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

[0033] The present invention is based on the optimization and transformation of the existing Grid-type-PDN structure obtained by periodically cutting off the power line and the ground line. figure 1 It is a schematic diagram of the structure of the on-chip power distribution network according to the embodiment of the present invention. Due to the limitation of the process and the consideration of signal integrity, the co-simulation optimization method of the on-chip power distribution network of the present invention is only for figure 1 In the edge area of ​​the power line and ground line, the structural variable parameter values ​​of the rest of the on-chip power distribution network are in figure 1 Both have been identified, and their material is set to copper.

[0034] The length, width and depth of the pixel blocks in the area to be optimized in...

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Abstract

The invention discloses a joint simulation optimization method for an on-chip power supply distribution network. The joint simulation optimization method comprises the following steps of 1, initializing parameters; 2, forming an EBG structure with different zigzag edges, and forming a population; generating EBG model scripts of different optimization areas, generating models according to script files and simulating, and transmitting back the S parameters obtained through EBG model simulation of each individual in the population to a main program; 3, calculating the fitness value of each individual sensor model; 4, updating an individual optimal value; and 5, updating the optimal value of the population; 6, judging whether the number of iterations reaches the maximum number of iterations or not; if not, repeating the steps 2 to 5; if yes, outputting the optimized EBG structure, and ending optimization; 7, combining the obtained EBG structures, and modeling again to obtain an optimized PDN structure; and 8, ending the joint simulation. According to the method, the EBG structures with excellent performance and the PDN layout formed by the EBG structures can be efficiently, reliably and automatically obtained.

Description

technical field [0001] The invention belongs to the technical field of chip packaging, and in particular relates to a co-simulation optimization method of an on-chip power distribution network with better noise suppression performance. Background technique [0002] With the rapid development of integrated circuit technology and system-in-package technology, the computing speed of high-speed hybrid circuits continues to accelerate, and the information throughput continues to increase. The resulting signal integrity (Signal Integrity, SI) and power integrity (Power Integrity) , PI) and electromagnetic compatibility (Electromagnetic Compatibility, EMC) problems have become increasingly serious. Therefore, how to effectively suppress the noise propagation in the high-speed hybrid circuit system while ensuring the SI and PI performance of the system has become an urgent problem to be solved. In this scenario, the design of the on-chip power distribution network has also become an...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/20
CPCG06F30/20
Inventor 方宇浩赵文生王大伟
Owner HANGZHOU DIANZI UNIV
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