Lookup table optimization for programming languages that target synchronous digital circuits

Abstract

A programming language and a compiler are disclosed that optimize the use of look-up tables (LUTs) on a synchronous digital circuit (SDC) such as a field programmable gate array (FPGA) that has been programmed. LUTs are optimized by merging multiple computational operations into the same LUT. A compiler parses source code into an intermediate representation (IR). Each node of the IR that represents an operator (e.g. '&', '+') is mapped to a LUT that implements that operator. The compiler iteratively traverses the IR, merging adjacent LUTs into a LUT that performs both operations and performing input removal optimizations. Additional operators may be merged into a merged LUT until all the LUT's inputs are assigned. Pipeline stages are then generated based on merged LUTs, and an SDC is programmed based on the pipeline and the merged LUT.

Description

Background technique [0001] A Hardware Description Language ("HDL") is a modeling language used by hardware engineers to describe the structure and behavior of electronic circuits, most of which are typically digital logic circuits. Examples of HDLs include Very High Speed ​​Integrated Circuit ("VHSIC") HDL and VERILOG. [0002] HDL typically requires many lines of code to simulate digital logic circuits. Even for hardware engineers who are very familiar with HDL, creating this kind of code is very time consuming. Furthermore, the more lines of code there are in a design, the more likely the design contains bugs or performs poorly. [0003] Because HDLs typically utilize a different programming paradigm than imperative programming languages, it is often difficult for software engineers not very familiar with HDLs to take advantage of these languages. As a result, electronic circuits generated from HDL created by software engineers may also contain errors or perform poorly. ...

AI Technical Summary

Problems solved by technology

Even for hardware engineers who are very familiar with HDL, creating this kind of code is very time consuming

Also, the more lines of code there are in the design, the more likely the design contains bugs or performs poorly

[0003] Because HDLs typically utilize a different programming paradigm than imperative programming languages, it is often difficult for software engineers not very familiar with HDLs to take advantage of these languages

As a result, electronic circuits generated from HDL created by software engineers may also contain errors or perform poorly

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