Formation method of semiconductor device

Abstract

The invention discloses a formation method of a semiconductor device, which comprises the steps of providing a to-be-etched layer, wherein the to-be-etched layer comprises a first region and a second region which are adjacent to each other, and the first region is adjacent to the second region; sequentially forming a first mask layer and a patterned core layer on the layer to be etched; forming side a wall material layer on the top and side wall surfaces of the core layer and the surface of the first mask layer; forming a first sacrificial layer on the side wall material layer on the surface of the first mask layer in the second region; forming a second sacrificial layer on the side wall material layer, wherein the second sacrificial layer exposes the top of the side wall material layer on the top surface of the core layer and the top of the first sacrificial layer; removing the first sacrificial layer, the side wall material layer on the surface of the first mask layer in the second region and the side wall material layer on the top surface of the core layer; removing the core layer; etching the first mask layer in the first region to form a first groove; and etching the first mask layer in the second region to form a second groove. According to the formation method provided by the invention, a smaller HHT size can be realized, and the obtained HHT size conforms to an expected target.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor device. Background technique [0002] With the improvement of circuit integration and the increase of scale, the size of unit devices in the circuit continues to shrink, and the requirements for integrated circuit manufacturing processes continue to increase. For example, the critical dimensions continue to decrease, and chip manufacturing requires more and more lithographic resolution high. With the continuous shrinking of the design size, the minimum resolution of the design pattern has exceeded the limit capability of the existing optical lithography platform. The industry has adopted a variety of technical solutions to solve this technical problem. According to the international semiconductor technology blueprint, Technology solutions such as dual patterning technology (DPT), extreme ultraviolet technology (EUV), and e...

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Problems solved by technology

[0005] However, when filling metal in the first groove to form the first metal line, the sidewall existing on the inner wall of the first groove will affect the distance (Head to Head, HTH) between the ends of the formed adjacent first metal line, resulting in the formed The HTH size between adjacent first metal lines is relatively large, and the formed HTH size does not meet the expected target

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