Formation method of semiconductor structure

Abstract

The invention discloses a formation method of a semiconductor structure, which comprises the steps of providing a substrate, wherein the substrate comprises a first region; forming a first gate structure and an initial first side wall structure located on the top surface and the side wall surface of the first gate structure in the first region, wherein the initial first side wall structure comprises an initial first side wall and an initial second side wall, and the material of the initial first side wall is different from that of the initial second side wall; forming a dielectric layer covering the side wall surface of the initial first side wall structure on the substrate, wherein the top surface of the dielectric layer is lower than the top surface of the initial first side wall structure; adopting a first etching process to remove the initial second side wall higher than the top surface of the dielectric layer, exposing the top surface and the side wall surface of the initial first side wall, and enabling the initial second side wall to form a second side wall; and removing the initial first side wall higher than the top surface of the dielectric layer by adopting a second etching process so as to enable the initial first side wall to form a first side wall. The method is beneficial to improving the performance of the formed semiconductor structure.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration. The fin field effect transistor is a common multi-gate device. The structure of the fin field effect transistor includes: a fin located on the surface of the semiconductor substrate and a barrier layer, the barrier layer covers part of the sidewall of the fin, and The surface of the barrier layer is lower than the top of the fin; the gate structure is located on the surface of the barrier layer and the top and sidewall surfaces of the fin; the source region and the drain region are located in the fin on both sides of the gate structure. [0003] Since the dielectric layer manufacturing process has a decisive effect on the h...

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Problems solved by technology

[0004] However, the sidewall formed by the existing dielectric layer process has poor morphology and defects, resulting in poor performance of the formed semiconductor

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