Method and apparatus for improved data transfer between processor cores

Abstract

The present invention relates to methods and apparatus for improved data transfer between processor cores. Interconnects achieve improved signal integrity even at high clock rates, and enable increased bandwidth and lower latency. In the interconnect, the sending processing core sends the data to the receiving core by forming a header indicating the location of the receiving core and the payload is a packet of data to be sent. Packets are sent to a data vortex switch on the same chip as the array of processing cores, which are routed to the receiving core by routing the packet to the array of processing cores that contains the receiving processing core. A data vortex switch routes packets to receiving processor cores in an array of processor cores. The Data Vortex switch is not a crossbar switch, which eliminates the global setup and reset of the Data Vortex switch as packets from different groups enter the switch. The data vortex switch and the processing core array are mounted on the same chip to reduce power and latency.

Description

[0001] Cross-reference of related patents [0002] This application claims priority to US Provisional Patent Application No. 62 / 778,354, filed on December 12, 2018, entitled "Data Transfer Between The Cores In A Microprocessor," which is incorporated herein by reference in its entirety. The disclosed systems and methods of operation also relate to subject matter disclosed in the following patents, which are hereby incorporated by reference in their entirety: (1) US Patent No. Coke S. Reed entitled "A Multiple Level Minimum Logic Network". 5,996,020; (2) U.S. Patent No. 6,289,021 entitled "A Scalable Low Latency Switch For Usage in an Interconnect Structure" by John Hesse; (3) U.S. Patent entitled "Multiple Path Wormhole Interconnect" by John Hesse No. 6,754,207, US Patent No. 9,954,797, entitled "Parallel Data Switch," by Coke S. Reed and Davis Murphy. technical field [0003] The present invention relates to a method and apparatus for improved data transfer between processor...

AI Technical Summary

Problems solved by technology

These techniques have been used to connect cores on a chip, but are not very effective at transferring data from a core on a first processor to a core on a second processor

In addition to the difficulties due to the mesh structure, in multi-chip applications, the use of long packets that pass through crossbar switches that carry data between chips also presents additional difficulties

Long packets lead to low bandwidth, high latency, limited scalability and high congestion

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