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Integrated circuit

A technology of integrated circuits and microelectronics, applied in circuits, electrical components, electrical solid-state devices, etc., can solve problems such as rising costs

Inactive Publication Date: 2004-01-14
CONVERSANT INTPROP MANAGEMENT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, forming a new mold cladding layer on the substrate will increase the cost

Method used

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Embodiment Construction

[0028] The present invention will be described in detail below according to the accompanying drawings.

[0029] figure 1 It is a diagram for explaining the calculation of the parasitic capacitance generated by the mold compound material of the semiconductor package device of the present invention, and shows a cross-sectional structure of a CMOS semiconductor device. according to figure 1 The semiconductor packaging device is formed on the surface of the silicon substrate 10 by a common CMOS manufacturing process, such as a P-type well (Well) 12, an n-type well (Well) 14, a field oxide film 16, a gate oxide film 18, Gate (gate) electrode 20, sidewall liner 22, source (Source) / drain impurity region 24; form a semiconductor tube; form a flat first interlayer insulating layer 26; in the source / drain of the above-mentioned semiconductor A contact point is formed on the impurity region 24; a source / drain electrode is formed on the primary metal wiring 28; and a flat second interla...

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Abstract

High speed integrated circuits are designed and fabricated by taking into account the capacitive loading on the integrated circuit by the integrated circuit potting material. Line drivers may be sized to drive conductive lines as capacitively loaded by the potting material. Repeaters may be provided along long lines, to drive the lines as capacitively loaded by the potting material. Intelligent drivers may sense the load due to the potting material and drive the lines as capacitively loaded by the potting material. The thickness of the passivating layer on the outer conductive lines may also be increased so as to prevent the potting material from extending between the conductive lines. High speed potted integrated circuits may thereby be provided.

Description

technical field [0001] The present invention relates to an integrated circuit, in particular to a semiconductor package (Package) device, and more particularly to calculation of the parasitic capacitance generated by the formed substance on the metal wiring, and to reduce the parasitic capacitance according to the analysis of the calculated parasitic capacitance. A semiconductor package device that reduces the parasitic capacitance of the metal wiring or increases the driving capability of the metal wiring to speed up the operation. Background technique [0002] Generally speaking, semiconductor packaging devices form circuits on semiconductor wafer (Wafer) substrates through multiple processes such as diffusion, growth, ion implantation, deposition, and photolithography. In order to make the formed circuits electrically connected, at least More than one metal wiring, and then, a protective film is coated on the metal wiring to protect the metal wiring, and then the wafer is...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768G02F1/136H01L23/522H01L29/786
CPCY10S257/923H01L23/5222H01L2924/0002H01L2924/00G02F1/136H01L29/786
Inventor 宋敏圭
Owner CONVERSANT INTPROP MANAGEMENT INC